target/rockchip: rk3566 add ynnnas
This commit is contained in:
Liangbin Lian
parent
8443ba7c3d
commit
232a915212
542
target/linux/rockchip/dts/rk3568/rk3566-ynnnas.dts
Normal file
542
target/linux/rockchip/dts/rk3568/rk3566-ynnnas.dts
Normal file
@ -0,0 +1,542 @@
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <dt-bindings/input/rk-input.h>
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#include <dt-bindings/sensor-dev.h>
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#include "rk3566.dtsi"
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/ {
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model = "Yingniuniu NAS";
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compatible = "ynn,nas", "rockchip,rk3566";
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aliases {
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led-boot = &sys_led;
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led-failsafe = &sys_led;
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led-running = &sys_led;
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led-upgrade = &sys_led;
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};
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <1>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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debug: debug@fd904000 {
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compatible = "rockchip,debug";
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reg = <0x0 0xfd904000 0x0 0x1000>,
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<0x0 0xfd905000 0x0 0x1000>,
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<0x0 0xfd906000 0x0 0x1000>,
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<0x0 0xfd907000 0x0 0x1000>;
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};
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cspmu: cspmu@fd90c000 {
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compatible = "rockchip,cspmu";
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reg = <0x0 0xfd90c000 0x0 0x1000>,
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<0x0 0xfd90d000 0x0 0x1000>,
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<0x0 0xfd90e000 0x0 0x1000>,
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<0x0 0xfd90f000 0x0 0x1000>;
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};
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dc_12v: dc-12v {
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compatible = "regulator-fixed";
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regulator-name = "dc_12v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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};
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vcc3v3_sys: vcc3v3-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_sys: vcc5v0-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vdd_cpu: vdd-cpu {
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compatible = "pwm-regulator";
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pwms = <&pwm0 0 5000 1>;
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regulator-name = "vdd_cpu";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1200000>;
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regulator-init-microvolt = <950000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-ramp-delay = <6001>;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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status = "okay";
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};
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vdd_logic: vdd-logic {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 5000 1>;
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regulator-name = "vdd_logic";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1100000>;
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regulator-init-microvolt = <950000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-ramp-delay = <6001>;
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regulator-settling-time-up-us = <250>;
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pwm-supply = <&vcc5v0_sys>;
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status = "okay";
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};
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vcc_1v8: vcc-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vcca_1v8: vcca-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "vcca_1v8";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vcc_3v3: vcc-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vcc3v3_sys>;
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};
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vcc5v0_usb: vcc5v0-usb {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_usb";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&dc_12v>;
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};
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vcc5v0_host: vcc5v0-host-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_host_en>;
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regulator-name = "vcc5v0_host";
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regulator-always-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&vcc5v0_usb>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 =
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<&led_user_pin>,
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<&led_sys_pin>,
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<&led_hdd_pin>,
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<&led_net_pin>;
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user_led: led-0 {
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label = "green:user";
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gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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sys_led: led-1 {
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label = "green:sys";
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gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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};
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hdd_led: led-2 {
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label = "green:hdd";
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gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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net_led: led-3 {
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label = "green:net";
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gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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/*
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pwm-leds {
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compatible = "pwm-leds";
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work_led: led-0 {
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label = "sys:green";
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pwms = <&pwm4 0 50000>;
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max-brightness = <255>;
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default-state = "on";
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};
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};
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*/
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adc_keys: adc-keys {
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compatible = "adc-keys";
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io-channels = <&saradc 0>;
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io-channel-names = "buttons";
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keyup-threshold-microvolt = <1800000>;
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poll-interval = <100>;
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back-key {
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label = "back";
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linux,code = <KEY_BACK>;
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press-threshold-microvolt = <1305500>;
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};
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};
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};
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&rng {
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status = "okay";
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};
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&wdt {
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snps,stop-on-shutdown;
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};
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// ynnnas-lp4x.dts
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&reserved_memory {
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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};
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&rockchip_suspend {
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status = "okay";
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};
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// ynnnas.dtsi
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&bus_npu {
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bus-supply = <&vdd_logic>;
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pvtm-supply = <&vdd_cpu>;
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status = "okay";
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};
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&cpu0 {
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cpu-supply = <&vdd_cpu>;
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};
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&dfi {
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status = "okay";
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};
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&dmc {
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center-supply = <&vdd_logic>;
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status = "okay";
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};
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&iep {
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status = "okay";
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};
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&iep_mmu {
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status = "okay";
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};
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&jpegd {
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status = "okay";
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};
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&jpegd_mmu {
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status = "okay";
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};
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&mpp_srv {
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status = "okay";
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};
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&nandc0 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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nand@0 {
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reg = <0>;
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-ecc-strength = <16>;
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nand-ecc-step-size = <1024>;
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};
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};
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/*
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* There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
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* 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
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* 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
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* must be consistent with the software configuration correspondingly
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* a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
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* should also be configured to 1.8V accordingly;
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* b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
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* should also be configured to 3.3V accordingly;
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* 3/ VCCIO2 voltage control selection (0xFDC20140)
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* BIT[0]: 0x0: from GPIO_0A7 (default)
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* BIT[0]: 0x1: from GRF
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* Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
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* L:VCCIO2 must supply 3.3V
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* H:VCCIO2 must supply 1.8V
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*/
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&pmu_io_domains {
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status = "okay";
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pmuio1-supply = <&vcc_3v3>;
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pmuio2-supply = <&vcc_3v3>;
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vccio1-supply = <&vcc_1v8>;
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vccio3-supply = <&vcc_3v3>;
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vccio4-supply = <&vcc_1v8>;
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vccio5-supply = <&vcc_3v3>;
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vccio6-supply = <&vcc_1v8>;
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vccio7-supply = <&vcc_3v3>;
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};
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&pwm0 {
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status = "okay";
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};
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&pwm1 {
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status = "okay";
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};
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/*
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&pwm4 {
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status = "okay";
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};
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*/
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&rk_rga {
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status = "okay";
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};
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&rkvdec {
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status = "okay";
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};
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&rkvdec_mmu {
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status = "okay";
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};
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&rkvenc {
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venc-supply = <&vdd_logic>;
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status = "okay";
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};
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&rkvenc_mmu {
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status = "okay";
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};
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&rknpu {
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rknpu-supply = <&vdd_logic>;
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status = "okay";
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};
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&rknpu_mmu {
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status = "okay";
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};
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&saradc {
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status = "okay";
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vref-supply = <&vcca_1v8>;
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};
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&sdhci {
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bus-width = <8>;
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supports-emmc;
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non-removable;
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max-frequency = <200000000>;
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status = "okay";
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};
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&tsadc {
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status = "okay";
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};
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&sata2 {
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status = "okay";
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};
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&u2phy0_host {
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phy-supply = <&vcc5v0_host>;
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status = "okay";
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};
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&u2phy0_otg {
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vbus-supply = <&vcc5v0_sys>;
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status = "okay";
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};
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&usb2phy0 {
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status = "okay";
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};
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&usbdrd_dwc3 {
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dr_mode = "otg";
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extcon = <&usb2phy0>;
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status = "okay";
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};
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&usbdrd30 {
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status = "okay";
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};
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&usbhost_dwc3 {
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status = "okay";
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};
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&usbhost30 {
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status = "okay";
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};
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&vdpu {
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status = "okay";
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};
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&vdpu_mmu {
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status = "okay";
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};
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&vepu {
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status = "okay";
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};
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&vepu_mmu {
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status = "okay";
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};
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// ynnnas-lp4x.dtsi
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&combphy1_usq {
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assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
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assigned-clock-rates = <100000000>;
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status = "okay";
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};
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&combphy2_psq {
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pinctrl-names = "default";
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pinctrl-0 = <&sata_pm_reset>;
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status = "okay";
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};
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&gmac1 {
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phy-mode = "rgmii";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
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//assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus
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&gmac1m1_clkinout>;
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tx_delay = <0x4f>;
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rx_delay = <0x2d>;
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phy-handle = <&rgmii_phy1>;
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status = "okay";
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};
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&mdio1 {
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rgmii_phy1: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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&pinctrl {
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pmic {
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pmic_int: pmic_int {
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rockchip,pins =
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<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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soc_slppin_gpio: soc_slppin_gpio {
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rockchip,pins =
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<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
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};
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|
||||
soc_slppin_slp: soc_slppin_slp {
|
||||
rockchip,pins =
|
||||
<0 RK_PA2 1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
soc_slppin_rst: soc_slppin_rst {
|
||||
rockchip,pins =
|
||||
<0 RK_PA2 2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
stata {
|
||||
sata_pm_reset: sata-pm-reset {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
led_user_pin: led-user-pin {
|
||||
rockchip,pins =
|
||||
<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
led_sys_pin: led-sys-pin {
|
||||
rockchip,pins =
|
||||
<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
led_hdd_pin: led-hdd-pin {
|
||||
rockchip,pins =
|
||||
<3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
led_net_pin: led-net-pin {
|
||||
rockchip,pins =
|
||||
<3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
64
target/linux/rockchip/dts/rk3568/rk3566.dtsi
Normal file
64
target/linux/rockchip/dts/rk3568/rk3566.dtsi
Normal file
@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
/delete-property/ ethernet0;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
/delete-node/ opp-1992000000;
|
||||
};
|
||||
|
||||
&lpddr4_params {
|
||||
/* freq info, freq_0 is final frequency, unit: MHz */
|
||||
freq_0 = <1056>;
|
||||
};
|
||||
|
||||
&lpddr4x_params {
|
||||
/* freq info, freq_0 is final frequency, unit: MHz */
|
||||
freq_0 = <1056>;
|
||||
};
|
||||
|
||||
&power {
|
||||
pd_pipe@RK3568_PD_PIPE {
|
||||
reg = <RK3568_PD_PIPE>;
|
||||
clocks = <&cru PCLK_PIPE>;
|
||||
pm_qos = <&qos_pcie2x1>,
|
||||
<&qos_sata1>,
|
||||
<&qos_sata2>,
|
||||
<&qos_usb3_0>,
|
||||
<&qos_usb3_1>;
|
||||
};
|
||||
};
|
||||
|
||||
&rkisp {
|
||||
rockchip,iq-feature = /bits/ 64 <0x3FBF7FE67FF>;
|
||||
};
|
||||
|
||||
&usbdrd_dwc3 {
|
||||
phys = <&u2phy0_otg>;
|
||||
phy-names = "usb2-phy";
|
||||
extcon = <&usb2phy0>;
|
||||
maximum-speed = "high-speed";
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,usb2-lpm-disable;
|
||||
};
|
||||
|
||||
/delete-node/ &combphy0_us;
|
||||
/delete-node/ &gmac0_clkin;
|
||||
/delete-node/ &gmac0_xpcsclk;
|
||||
/delete-node/ &gmac0;
|
||||
/delete-node/ &pcie30_phy_grf;
|
||||
/delete-node/ &pcie30phy;
|
||||
/delete-node/ &pcie3x1;
|
||||
/delete-node/ &pcie3x2;
|
||||
/delete-node/ &qos_pcie3x1;
|
||||
/delete-node/ &qos_pcie3x2;
|
||||
/delete-node/ &qos_sata0;
|
||||
/delete-node/ &sata0;
|
||||
Loading…
Reference in New Issue
Block a user