From 37a6e9805ffa0eb0dc67d2bf44af9f0bdd2ceafd Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Wed, 27 Aug 2025 13:31:02 +0800 Subject: [PATCH] target/rockchip: add friendlyelec nanopi r76s support --- .../armv8/base-files/etc/board.d/01_leds | 1 + .../armv8/base-files/etc/board.d/02_network | 1 + .../dts/rk3576/rk3576-nanopi-r76s.dts | 261 +++++++ .../dts/rk3576/rk3576-nanopi5-common.dtsi | 643 ++++++++++++++++++ .../dts/rk3576/rk3576-no-power-domain.dtsi | 123 ++++ .../rockchip/dts/rk3576/rk3576-patch.dtsi | 209 ++++++ .../rockchip/dts/rk3576/rk3576-rk806.dtsi | 381 +++++++++++ .../dts/rk3576/update-power-domain.sh | 109 +++ target/linux/rockchip/image/legacy.mk | 19 + .../rockchip/image/legacy/rk3576.bootscript | 12 + 10 files changed, 1759 insertions(+) create mode 100644 target/linux/rockchip/dts/rk3576/rk3576-nanopi-r76s.dts create mode 100644 target/linux/rockchip/dts/rk3576/rk3576-nanopi5-common.dtsi create mode 100644 target/linux/rockchip/dts/rk3576/rk3576-no-power-domain.dtsi create mode 100644 target/linux/rockchip/dts/rk3576/rk3576-patch.dtsi create mode 100644 target/linux/rockchip/dts/rk3576/rk3576-rk806.dtsi create mode 100755 target/linux/rockchip/dts/rk3576/update-power-domain.sh create mode 100644 target/linux/rockchip/image/legacy/rk3576.bootscript diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index 6a68c01e59..8d932dfd6a 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -16,6 +16,7 @@ friendlyarm,nanopi-r4s|\ friendlyarm,nanopi-r4se|\ friendlyarm,nanopi-r4s-enterprise|\ friendlyarm,nanopi-r6c|\ +friendlyarm,nanopi-r76s|\ xunlong,orangepi-r1-plus|\ xunlong,orangepi-r1-plus-lts) ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0" diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index bc1787e98e..0779a7b22b 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -18,6 +18,7 @@ rockchip_setup_interfaces() friendlyarm,nanopi-r4se|\ friendlyarm,nanopi-r4s-enterprise|\ friendlyarm,nanopi-r6c|\ + friendlyarm,nanopi-r76s|\ hinlink,opc-h66k|\ hinlink,h88k-v2|\ hinlink,h88k|\ diff --git a/target/linux/rockchip/dts/rk3576/rk3576-nanopi-r76s.dts b/target/linux/rockchip/dts/rk3576/rk3576-nanopi-r76s.dts new file mode 100644 index 0000000000..6e2d88aa66 --- /dev/null +++ b/target/linux/rockchip/dts/rk3576/rk3576-nanopi-r76s.dts @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + */ + +/dts-v1/; + +#include "rk3576-nanopi5-common.dtsi" + +/ { + model = "FriendlyElec NanoPi R76S"; + compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576"; + eth_order = "0001:21:00.0,0000:01:00.0"; + + aliases { + ethernet0 = &r8125_b; + ethernet1 = &r8125_a; + + led-boot = &sys_led; + led-failsafe = &sys_led; + led-running = &sys_led; + led-upgrade = &sys_led; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = ; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + lan_led: led-1 { + gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + label = "green:lan"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_pin>; + }; + + wan_led: led-2 { + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "green:wan"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&mach { + hwrev = <0x02>; + model = "NanoPi R76S"; +}; + +&mdio0 { + status = "disabled"; +}; + +&mdio1 { + status = "disabled"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&adc1_keys { + status = "disabled"; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c5m3_xfer>; +}; + +&i2c8 { + clock-frequency = <200000>; + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&pinctrl { + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie0_reset_gpio: pcie0-reset-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie1_reset_gpio: pcie1-reset-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pcie0 { + status = "okay"; + pinctrl-0 = <&pcie0_reset_gpio>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + rockchip,skip-scan-in-resume; + rockchip,skip-hw-retry; + rockchip,wait-for-link-ms = <1000>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + /delete-property/ prsnt-gpios; + + pcie@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_a: pcie@0,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_reset_gpio>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + rockchip,skip-hw-retry; + rockchip,wait-for-link-ms = <1000>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + + pcie@0,0 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_b: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&sata0 { + status = "disabled"; +}; + +&sdio_pwrseq { + status = "okay"; +}; + +&sdio { + status = "okay"; + vqmmc-supply = <&vcc_1v8_s0>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + + rtl8822cs@1 { + reg = <1>; + compatible = "realtek,rtl8822cs"; + }; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + }; +}; + +&ufshc { + status = "disabled"; +}; + +&u2phy1 { + status = "disabled"; +}; + +&u2phy1_otg { + status = "disabled"; +}; + +&usb_drd1_dwc3 { + status = "disabled"; +}; + +&vcc5v0_host { + status = "disabled"; +}; + +&spi0 { + status = "disabled"; + + spidev0: spidev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "disabled"; + }; +}; + +&sai1 { + status = "disabled"; +}; + +&uart6 { + status = "okay"; +}; diff --git a/target/linux/rockchip/dts/rk3576/rk3576-nanopi5-common.dtsi b/target/linux/rockchip/dts/rk3576/rk3576-nanopi5-common.dtsi new file mode 100644 index 0000000000..f35c3201b5 --- /dev/null +++ b/target/linux/rockchip/dts/rk3576/rk3576-nanopi5-common.dtsi @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyelec.com) + * + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include "rk3576-patch.dtsi" +#include "rk3576-rk806.dtsi" + +/ { + model = "FriendlyElec boards based on Rockchip RK3576"; + compatible = "friendlyelec,nanopi5", + "rockchip,rk3576"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &sdhci; + scsi0 = &lun0; + scsi1 = &lun1; + scsi2 = &lun2; + scsi3 = &lun3; + }; + + chosen: chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc0_keys: adc0-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-down-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + adc1_keys: adc1-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + mach: board { + compatible = "friendlyelec,board"; + machine = "NANOPI-M5"; + hwrev = <255>; + model = "NanoPi M5 Series"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_poweren_gpio>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + simple_bat: battery { + compatible = "simple-battery"; + voltage-max-design-microvolt = <21000000>; + voltage-min-design-microvolt = <4500000>; + }; + + simple_vin: simple-vin { + compatible = "simple-adc-power-v2"; + io-channels = <&saradc 2>; + io-channel-names = "voltage"; + monitored-battery = <&simple_bat>; + }; + + test-power { + status = "okay"; + }; + + vcc_1v8_s0: vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc1v8_ufs_vccq2_s0: vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc1v2_ufs_vccq_s0: vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_device>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren>; + }; + + /* + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; + */ + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_device: vcc5v0-device { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_2v0_pldo_s3: vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_m2_keym: vcc3v3-m2_keym { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_pwren>; + regulator-name = "vcc3v3_m2_keym"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&crypto { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus>; + + tx_delay = <0x21>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <ð1m0_miim + ð1m0_tx_bus2 + ð1m0_rx_bus2 + ð1m0_rgmii_clk + ð1m0_rgmii_bus>; + + tx_delay = <0x20>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m1_xfer>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + interrupt-parent = <&gpio2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_int>; + realtek,ledsel = <0xae00>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC1_OUT>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_int>; + realtek,ledsel = <0xae00>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_prsnt>; + prsnt-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + rockchip,skip-hw-retry; + rockchip,wait-for-link-ms = <1000>; + vpcie3v3-supply = <&vcc3v3_m2_keym>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + gmac0_int: gmac0-int { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gmac1_int: gmac1-int { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_m2_pwren: pcie-m2-pwren { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_m2_prsnt: pcie-m20-prsnt { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + /omit-if-no-ref/ + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + /omit-if-no-ref/ + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren: usb-otg0-pwren { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sai1m0_lrck + &sai1m0_sclk + &sai1m0_sdi0 + &sai1m0_sdo0>; +}; + +&sai6 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdio { + max-frequency = <200000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + status = "disabled"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + phy-supply = <&vbus5v0_typec>; +}; + +&u2phy1_otg { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&uart0 { + status = "okay"; +}; + +&ufshc { + status = "okay"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + + scsi { + #address-cells = <1>; + #size-cells = <0>; + + lun0: lun@0 { + reg = <0>; + }; + + lun1: lun@1 { + reg = <1>; + }; + + lun2: lun@2 { + reg = <2>; + }; + + lun3: lun@3 { + reg = <3>; + }; + }; +}; + +&usbdp_phy { + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/target/linux/rockchip/dts/rk3576/rk3576-no-power-domain.dtsi b/target/linux/rockchip/dts/rk3576/rk3576-no-power-domain.dtsi new file mode 100644 index 0000000000..fa14385916 --- /dev/null +++ b/target/linux/rockchip/dts/rk3576/rk3576-no-power-domain.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree override to remove power-domains properties + * Auto-generated on 2025-08-27 07:08:04 UTC + * Source: ../../files/arch/arm64/boot/dts/rockchip/rk3576.dtsi + */ + +&power { + status = "disabled"; +}; + +&gmac0 { + /delete-property/ power-domains; +}; + +&gmac1 { + /delete-property/ power-domains; +}; + +&gpu { + /delete-property/ power-domains; +}; + +&hdmi { + /delete-property/ power-domains; +}; + +&pcie0 { + /delete-property/ power-domains; +}; + +&pcie1 { + /delete-property/ power-domains; +}; + +&sai0 { + /delete-property/ power-domains; +}; + +&sai1 { + /delete-property/ power-domains; +}; + +&sai2 { + /delete-property/ power-domains; +}; + +&sai3 { + /delete-property/ power-domains; +}; + +&sai4 { + /delete-property/ power-domains; +}; + +&sai5 { + /delete-property/ power-domains; +}; + +&sai6 { + /delete-property/ power-domains; +}; + +&sai7 { + /delete-property/ power-domains; +}; + +&sai8 { + /delete-property/ power-domains; +}; + +&sai9 { + /delete-property/ power-domains; +}; + +&sata0 { + /delete-property/ power-domains; +}; + +&sata1 { + /delete-property/ power-domains; +}; + +&sdhci { + /delete-property/ power-domains; +}; + +&sdio { + /delete-property/ power-domains; +}; + +&sdmmc { + /delete-property/ power-domains; +}; + +&sfc0 { + /delete-property/ power-domains; +}; + +&sfc1 { + /delete-property/ power-domains; +}; + +&ufshc { + /delete-property/ power-domains; +}; + +&usb_drd0_dwc3 { + /delete-property/ power-domains; +}; + +&usb_drd1_dwc3 { + /delete-property/ power-domains; +}; + +&vop { + /delete-property/ power-domains; +}; + +&vop_mmu { + /delete-property/ power-domains; +}; + diff --git a/target/linux/rockchip/dts/rk3576/rk3576-patch.dtsi b/target/linux/rockchip/dts/rk3576/rk3576-patch.dtsi new file mode 100644 index 0000000000..eee4ce8819 --- /dev/null +++ b/target/linux/rockchip/dts/rk3576/rk3576-patch.dtsi @@ -0,0 +1,209 @@ +#include +#include "rk3576-no-power-domain.dtsi" + +/ { + thermal_zones: thermal-zones { + /* sensor near the center of the SoC */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor for cluster1 (big Cortex-A72 cores) */ + bigcore_thermal: bigcore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore_alert: bigcore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + bigcore_crit: bigcore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&bigcore_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + /* sensor for cluster0 (little Cortex-A53 cores) */ + littlecore_thermal: littlecore-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + littlecore_alert: littlecore-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&littlecore_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + gpu_alert: gpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr_thermal: ddr-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + ddr_crit: ddr-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + soc { + crypto: crypto@2a400000 { + compatible = "rockchip,crypto-v4"; + reg = <0x0 0x2a400000 0x0 0x2000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, + <&cru CLK_PKA_CRYPTO_NS>; + clock-names = "aclk", "hclk", "pka"; + assigned-clocks = <&cru ACLK_CRYPTO_NS>, <&cru CLK_PKA_CRYPTO_NS>; + assigned-clock-rates = <300000000>, <300000000>; + resets = <&cru SRST_H_CRYPTO_NS>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@2a410000 { + compatible = "rockchip,rkrng"; + reg = <0x0 0x2a410000 0x0 0x200>; + interrupts = ; + clocks = <&cru HCLK_TRNG_NS>; + clock-names = "hclk_trng"; + resets = <&cru SRST_H_TRNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + tsadc: tsadc@2ae70000 { + compatible = "rockchip,rk3576-tsadc"; + reg = <0x0 0x2ae70000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "disabled"; + }; + }; +}; + +&cpu_l1 { + #cooling-cells = <2>; +}; + +&cpu_l2 { + #cooling-cells = <2>; +}; + +&cpu_l3 { + #cooling-cells = <2>; +}; + +&cpu_b1 { + #cooling-cells = <2>; +}; + +&cpu_b2 { + #cooling-cells = <2>; +}; + +&cpu_b3 { + #cooling-cells = <2>; +}; diff --git a/target/linux/rockchip/dts/rk3576/rk3576-rk806.dtsi b/target/linux/rockchip/dts/rk3576/rk3576-rk806.dtsi new file mode 100644 index 0000000000..fab780f3dd --- /dev/null +++ b/target/linux/rockchip/dts/rk3576/rk3576-rk806.dtsi @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&i2c1 { + status = "okay"; + + rk806: pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/target/linux/rockchip/dts/rk3576/update-power-domain.sh b/target/linux/rockchip/dts/rk3576/update-power-domain.sh new file mode 100755 index 0000000000..3544b93a4f --- /dev/null +++ b/target/linux/rockchip/dts/rk3576/update-power-domain.sh @@ -0,0 +1,109 @@ +#!/bin/bash + +# Extract power-domains nodes from device tree and create override dtsi +# Usage: ./extract-power-domains.sh [output_dtsi] + +set -e + +INPUT_FILE="../../files/arch/arm64/boot/dts/rockchip/rk3576.dtsi" +OUTPUT_FILE="rk3576-no-power-domain.dtsi" + +if [ -z "$INPUT_FILE" ]; then + echo "Usage: $0 [output_dtsi]" + echo "Example: $0 rk3576.dtsi rk3576-no-power-domain.dtsi" + exit 1 +fi + +if [ ! -f "$INPUT_FILE" ]; then + echo "Error: Input file '$INPUT_FILE' not found" + exit 1 +fi + +echo "Analyzing $INPUT_FILE for nodes with power-domains properties..." + +# Create temporary file +TEMP_FILE=$(mktemp) + +# Extract node labels with power-domains property +# This approach is more reliable and simpler +grep -n "power-domains" "$INPUT_FILE" | while read -r line; do + line_num=$(echo "$line" | cut -d: -f1) + + # Look backward from the power-domains line to find the node definition + for ((i=line_num; i>=1; i--)); do + current_line=$(sed -n "${i}p" "$INPUT_FILE") + + # Skip empty lines and comments + if echo "$current_line" | grep -qE '^\s*(//|/\*|\*|$)'; then + continue + fi + + # Look for node definition with label + if echo "$current_line" | grep -qE '^\s*[a-zA-Z_][a-zA-Z0-9_]*\s*:'; then + # Extract just the label part (before the colon) + label=$(echo "$current_line" | grep -oE '[a-zA-Z_][a-zA-Z0-9_]*\s*:' | grep -oE '[a-zA-Z0-9_]*') + echo "$label" + break + fi + + # If we hit another closing brace, we've gone too far + if echo "$current_line" | grep -q '}' && [ $i -lt $((line_num - 1)) ]; then + break + fi + done +done | sort | uniq > "$TEMP_FILE" + +# Count found nodes +NODE_COUNT=$(wc -l < "$TEMP_FILE" 2>/dev/null || echo "0") + +if [ "$NODE_COUNT" -eq 0 ]; then + echo "No labeled nodes with power-domains property found in $INPUT_FILE" + rm -f "$TEMP_FILE" + exit 0 +fi + +echo "Found $NODE_COUNT labeled nodes with power-domains property:" +cat "$TEMP_FILE" | sed 's/^/ - /' + +# Generate the output dtsi file +echo "" +echo "Generating $OUTPUT_FILE..." + +# Create the header +cat > "$OUTPUT_FILE" << EOF +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device tree override to remove power-domains properties + * Auto-generated on $(date -u '+%Y-%m-%d %H:%M:%S') UTC + * Source: $INPUT_FILE + */ + +&power { + status = "disabled"; +}; + +EOF + +# Add delete-property statements for each node +while IFS= read -r label; do + if [ -n "$label" ]; then + cat >> "$OUTPUT_FILE" << EOF +&${label} { + /delete-property/ power-domains; +}; + +EOF + fi +done < "$TEMP_FILE" + +# Clean up +rm -f "$TEMP_FILE" + +echo "Successfully created $OUTPUT_FILE with $NODE_COUNT node overrides" +echo "" +echo "Usage: Include this file in your board dtsi with:" +echo " #include \"$OUTPUT_FILE\"" +echo "" +echo "Generated file contents:" +echo "========================" +cat "$OUTPUT_FILE" \ No newline at end of file diff --git a/target/linux/rockchip/image/legacy.mk b/target/linux/rockchip/image/legacy.mk index 2932c08468..92924a7699 100644 --- a/target/linux/rockchip/image/legacy.mk +++ b/target/linux/rockchip/image/legacy.mk @@ -170,6 +170,25 @@ endef TARGET_DEVICES += lyt_t68m +# RK3576 + +define Device/Legacy/rk3576 +$(call Device/Legacy,$(1)) + SOC := rk3576 + UBOOT_DEVICE_NAME := easepi-rk3576 + BOOT_SCRIPT := rk3576 + DEVICE_PACKAGES := kmod-rga3 kmod-rk_vcodec kmod-rkgpu-bifrost kmod-rknpu kmod-iio-rockchip-saradc +endef + +define Device/friendlyarm_nanopi-r76s +$(call Device/Legacy/rk3576,$(1)) + DEVICE_VENDOR := FriendlyARM + DEVICE_MODEL := NanoPi R76S + DEVICE_PACKAGES += kmod-r8169 kmod-hwmon-pwmfan kmod-thermal +endef +TARGET_DEVICES += friendlyarm_nanopi-r76s + + # RK3588 define Device/Legacy/rk3588 diff --git a/target/linux/rockchip/image/legacy/rk3576.bootscript b/target/linux/rockchip/image/legacy/rk3576.bootscript new file mode 100644 index 0000000000..b7194cbfa3 --- /dev/null +++ b/target/linux/rockchip/image/legacy/rk3576.bootscript @@ -0,0 +1,12 @@ +if test -z "${devtype}"; then + setenv devtype mmc +fi + +part uuid ${devtype} ${devnum}:2 uuid + +setenv bootargs "console=ttyS0,1500000 earlycon=uart8250,mmio32,0x2ad40000 root=PARTUUID=${uuid} rw rootwait" + +load ${devtype} ${devnum}:1 ${fdt_addr_r} rockchip.dtb +load ${devtype} ${devnum}:1 ${kernel_addr_r} kernel.img + +booti ${kernel_addr_r} - ${fdt_addr_r}