target/rockchip: add rockchip opp and pvtm

target/linux/rockchip/files/include/linux/rockchip/rockchip_sip.h

@@ -0,0 +1,549 @@
+/* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ROCKCHIP_SIP_H
+#define __ROCKCHIP_SIP_H
+
+#include <linux/arm-smccc.h>
+#include <linux/io.h>
+
+/* SMC function IDs for SiP Service queries, compatible with kernel-3.10 */
+#define SIP_ATF_VERSION			0x82000001
+#define SIP_ACCESS_REG			0x82000002
+#define SIP_SUSPEND_MODE		0x82000003
+#define SIP_PENDING_CPUS		0x82000004
+#define SIP_UARTDBG_CFG			0x82000005
+#define SIP_UARTDBG_CFG64		0xc2000005
+#define SIP_MCU_EL3FIQ_CFG		0x82000006
+#define SIP_ACCESS_CHIP_STATE64		0xc2000006
+#define SIP_SECURE_MEM_CONFIG		0x82000007
+#define SIP_ACCESS_CHIP_EXTRA_STATE64	0xc2000007
+#define SIP_DRAM_CONFIG			0x82000008
+#define SIP_SHARE_MEM			0x82000009
+#define SIP_SIP_VERSION			0x8200000a
+#define SIP_REMOTECTL_CFG		0x8200000b
+#define PSCI_SIP_VPU_RESET		0x8200000c
+#define SIP_BUS_CFG			0x8200000d
+#define SIP_LAST_LOG			0x8200000e
+#define SIP_SCMI_AGENT0			0x82000010
+#define SIP_SCMI_AGENT1			0x82000011
+#define SIP_SCMI_AGENT2			0x82000012
+#define SIP_SCMI_AGENT3			0x82000013
+#define SIP_SCMI_AGENT4			0x82000014
+#define SIP_SCMI_AGENT5			0x82000015
+#define SIP_SCMI_AGENT6			0x82000016
+#define SIP_SCMI_AGENT7			0x82000017
+#define SIP_SCMI_AGENT8			0x82000018
+#define SIP_SCMI_AGENT9			0x82000019
+#define SIP_SCMI_AGENT10		0x8200001a
+#define SIP_SCMI_AGENT11		0x8200001b
+#define SIP_SCMI_AGENT12		0x8200001c
+#define SIP_SCMI_AGENT13		0x8200001d
+#define SIP_SCMI_AGENT14		0x8200001e
+#define SIP_SCMI_AGENT15		0x8200001f
+#define SIP_SDEI_FIQ_DBG_SWITCH_CPU	0x82000020
+#define SIP_SDEI_FIQ_DBG_GET_EVENT_ID	0x82000021
+#define RK_SIP_AMP_CFG			0x82000022
+#define RK_SIP_FIQ_CTRL			0x82000024
+#define SIP_HDCP_CONFIG			0x82000025
+#define SIP_WDT_CFG			0x82000026
+#define SIP_HDMIRX_CFG			0x82000027
+#define SIP_MCU_CFG			0x82000028
+#define SIP_PVTPLL_CFG			0x82000029
+
+#define TRUSTED_OS_HDCPKEY_INIT		0xB7000003
+
+/* Rockchip Sip version */
+#define SIP_IMPLEMENT_V1                (1)
+#define SIP_IMPLEMENT_V2                (2)
+
+/* Trust firmware version */
+#define ATF_VER_MAJOR(ver)		(((ver) >> 16) & 0xffff)
+#define ATF_VER_MINOR(ver)		(((ver) >> 0) & 0xffff)
+
+/* SIP_ACCESS_REG: read or write */
+#define SECURE_REG_RD			0x0
+#define SECURE_REG_WR			0x1
+
+/* Fiq debugger share memory: 8KB enough */
+#define FIQ_UARTDBG_PAGE_NUMS		2
+#define FIQ_UARTDBG_SHARE_MEM_SIZE	((FIQ_UARTDBG_PAGE_NUMS) * 4096)
+
+/* Error return code */
+#define IS_SIP_ERROR(x)			(!!(x))
+
+#define SIP_RET_SUCCESS			0
+#define SIP_RET_SMC_UNKNOWN		-1
+#define SIP_RET_NOT_SUPPORTED		-2
+#define SIP_RET_INVALID_PARAMS		-3
+#define SIP_RET_INVALID_ADDRESS		-4
+#define SIP_RET_DENIED			-5
+#define SIP_RET_SET_RATE_TIMEOUT	-6
+
+/* SIP_UARTDBG_CFG64 call types */
+#define UARTDBG_CFG_INIT		0xf0
+#define UARTDBG_CFG_OSHDL_TO_OS		0xf1
+#define UARTDBG_CFG_OSHDL_CPUSW		0xf3
+#define UARTDBG_CFG_OSHDL_DEBUG_ENABLE	0xf4
+#define UARTDBG_CFG_OSHDL_DEBUG_DISABLE	0xf5
+#define UARTDBG_CFG_PRINT_PORT		0xf7
+#define UARTDBG_CFG_FIQ_ENABEL		0xf8
+#define UARTDBG_CFG_FIQ_DISABEL		0xf9
+
+/* SIP_SUSPEND_MODE32 call types */
+#define SUSPEND_MODE_CONFIG		0x01
+#define WKUP_SOURCE_CONFIG		0x02
+#define PWM_REGULATOR_CONFIG		0x03
+#define GPIO_POWER_CONFIG		0x04
+#define SUSPEND_DEBUG_ENABLE		0x05
+#define APIOS_SUSPEND_CONFIG		0x06
+#define VIRTUAL_POWEROFF		0x07
+#define SUSPEND_WFI_TIME_MS		0x08
+#define LINUX_PM_STATE			0x09
+#define SUSPEND_IO_RET_CONFIG		0x0a
+#define SLEEP_PIN_CONFIG		0x0b
+
+/* SIP_REMOTECTL_CFG call types */
+#define	REMOTECTL_SET_IRQ		0xf0
+#define REMOTECTL_SET_PWM_CH		0xf1
+#define REMOTECTL_SET_PWRKEY		0xf2
+#define REMOTECTL_GET_WAKEUP_STATE	0xf3
+#define REMOTECTL_ENABLE		0xf4
+/* wakeup state */
+#define REMOTECTL_PWRKEY_WAKEUP		0xdeadbeaf
+
+/* SIP_MCU_CFG child configs, MCU ID */
+enum {
+	RK_BUS_MCU,
+	RK_PMU_MCU,
+	RK_DDR_MCU,
+	RK_NPU_MCU,
+};
+
+#define RK_SIP_MCU_ID(type, id)		((type) << 8 | id)
+
+#define RK_SIP_CFG_BUSMCU_0_ID		RK_SIP_MCU_ID(RK_BUS_MCU, 0)
+#define RK_SIP_CFG_BUSMCU_1_ID		RK_SIP_MCU_ID(RK_BUS_MCU, 1)
+#define RK_SIP_CFG_PMUMCU_0_ID		RK_SIP_MCU_ID(RK_PMU_MCU, 0)
+#define RK_SIP_CFG_DDRMCU_0_ID		RK_SIP_MCU_ID(RK_DDR_MCU, 0)
+#define RK_SIP_CFG_NPUMCU_0_ID		RK_SIP_MCU_ID(RK_NPU_MCU, 0)
+
+/* SIP_MCU_CFG child configs */
+#define CONFIG_MCU_CODE_START_ADDR	0x01
+#define CONFIG_MCU_EXPERI_START_ADDR	0x02
+#define CONFIG_MCU_SRAM_START_ADDR	0x03
+#define CONFIG_MCU_EXSRAM_START_ADDR	0x04
+
+struct dram_addrmap_info {
+	u64 ch_mask[2];
+	u64 bk_mask[4];
+	u64 bg_mask[2];
+	u64 cs_mask[2];
+	u32 reserved[20];
+	u32 bank_bit_first;
+	u32 bank_bit_mask;
+};
+
+/* AMP Ctrl */
+enum {
+	RK_AMP_SUB_FUNC_CFG_MODE = 0,
+	RK_AMP_SUB_FUNC_BOOT_ARG01,
+	RK_AMP_SUB_FUNC_BOOT_ARG23,
+	RK_AMP_SUB_FUNC_REQ_CPU_OFF,
+	RK_AMP_SUB_FUNC_GET_CPU_STATUS,
+	RK_AMP_SUB_FUNC_RSV, /* for RTOS */
+	RK_AMP_SUB_FUNC_CPU_ON,
+	RK_AMP_SUB_FUNC_END,
+};
+
+enum {
+	FIRMWARE_NONE,
+	FIRMWARE_TEE_32BIT,
+	FIRMWARE_ATF_32BIT,
+	FIRMWARE_ATF_64BIT,
+	FIRMWARE_END,
+};
+
+/* Share mem page types */
+typedef enum {
+	SHARE_PAGE_TYPE_INVALID = 0,
+	SHARE_PAGE_TYPE_UARTDBG,
+	SHARE_PAGE_TYPE_DDR,
+	SHARE_PAGE_TYPE_DDRDBG,
+	SHARE_PAGE_TYPE_DDRECC,
+	SHARE_PAGE_TYPE_DDRFSP,
+	SHARE_PAGE_TYPE_DDR_ADDRMAP,
+	SHARE_PAGE_TYPE_LAST_LOG,
+	SHARE_PAGE_TYPE_HDCP,
+	SHARE_PAGE_TYPE_SLEEP,
+	SHARE_PAGE_TYPE_MAX,
+} share_page_type_t;
+
+/* fiq control sub func */
+enum {
+	RK_SIP_FIQ_CTRL_FIQ_EN = 1,
+	RK_SIP_FIQ_CTRL_FIQ_DIS,
+	RK_SIP_FIQ_CTRL_SET_AFF
+};
+
+/* hdcp function types */
+enum {
+	HDCP_FUNC_STORAGE_INCRYPT = 1,
+	HDCP_FUNC_KEY_LOAD,
+	HDCP_FUNC_ENCRYPT_MODE
+};
+
+/* support hdcp device list */
+enum {
+	DP_TX0,
+	DP_TX1,
+	EDP_TX0,
+	EDP_TX1,
+	HDMI_TX0,
+	HDMI_TX1,
+	HDMI_RX,
+	MAX_DEVICE,
+};
+
+/* SIP_WDT_CONFIG call types  */
+enum {
+	WDT_START = 0,
+	WDT_STOP = 1,
+	WDT_PING = 2,
+};
+
+/* SIP_HDMIRX_CONFIG child configs */
+enum {
+	HDMIRX_AUTO_TOUCH_EN = 0,
+	HDMIRX_REG_PRE_FETCH = 1,
+	HDMIRX_INFO_NOTIFY = 2,
+};
+
+/* SIP_PVTPLL_CFG child configs */
+enum {
+	PVTPLL_GET_INFO = 0,
+	PVTPLL_ADJUST_TABLE = 1,
+	PVTPLL_LOW_TEMP = 2,
+};
+
+struct pt_regs;
+typedef void (*sip_fiq_debugger_uart_irq_tf_cb_t)(struct pt_regs *_pt_regs, unsigned long cpu);
+
+/*
+ * Rules: struct arm_smccc_res contains result and data, details:
+ *
+ * a0: error code(0: success, !0: error);
+ * a1~a3: data
+ */
+#if IS_REACHABLE(CONFIG_ROCKCHIP_SIP)
+struct arm_smccc_res sip_smc_get_atf_version(void);
+struct arm_smccc_res sip_smc_get_sip_version(void);
+struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2);
+struct arm_smccc_res sip_smc_request_share_mem(u32 page_num,
+					       share_page_type_t page_type);
+struct arm_smccc_res sip_smc_mcu_el3fiq(u32 arg0, u32 arg1, u32 arg2);
+struct arm_smccc_res sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2);
+struct arm_smccc_res sip_smc_get_suspend_info(u32 info);
+struct arm_smccc_res sip_smc_lastlog_request(void);
+
+int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2);
+int sip_smc_virtual_poweroff(void);
+int sip_smc_remotectl_config(u32 func, u32 data);
+
+int sip_smc_secure_reg_write(u32 addr_phy, u32 val);
+u32 sip_smc_secure_reg_read(u32 addr_phy);
+struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2);
+struct dram_addrmap_info *sip_smc_get_dram_map(void);
+int sip_smc_amp_config(u32 sub_func_id, u32 arg1, u32 arg2, u32 arg3);
+struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id, u32 arg1);
+struct arm_smccc_res sip_smc_get_pvtpll_info(u32 sub_func_id, u32 arg1);
+struct arm_smccc_res sip_smc_pvtpll_config(u32 sub_func_id, u32 arg1, u32 arg2,
+					   u32 arg3, u32 arg4, u32 arg5, u32 arg6);
+
+void __iomem *sip_hdcp_request_share_memory(int id);
+struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2);
+ulong sip_cpu_logical_map_mpidr(u32 cpu);
+/***************************fiq debugger **************************************/
+void sip_fiq_debugger_enable_fiq(bool enable, uint32_t tgt_cpu);
+void sip_fiq_debugger_enable_debug(bool enable);
+int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id, sip_fiq_debugger_uart_irq_tf_cb_t callback_fn);
+int sip_fiq_debugger_set_print_port(u32 port_phyaddr, u32 baudrate);
+int sip_fiq_debugger_request_share_memory(void);
+int sip_fiq_debugger_get_target_cpu(void);
+int sip_fiq_debugger_switch_cpu(u32 cpu);
+int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu, u32 flag);
+int sip_fiq_debugger_is_enabled(void);
+int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag);
+int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data);
+int sip_wdt_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3);
+int sip_hdmirx_config(u32 sub_func, u32 arg1, u32 arg2, u32 arg3);
+int sip_hdcpkey_init(u32 hdcp_id);
+int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2);
+#else
+static inline struct arm_smccc_res sip_smc_get_atf_version(void)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_get_sip_version(void)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_dram(u32 arg0, u32 arg1, u32 arg2)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_request_share_mem
+			(u32 page_num, share_page_type_t page_type)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_mcu_el3fiq
+			(u32 arg0, u32 arg1, u32 arg2)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res
+sip_smc_vpu_reset(u32 arg0, u32 arg1, u32 arg2)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_get_suspend_info(u32 info)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_lastlog_request(void)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline int sip_smc_set_suspend_mode(u32 ctrl, u32 config1, u32 config2)
+{
+	return 0;
+}
+
+static inline int sip_smc_virtual_poweroff(void) { return 0; }
+static inline int sip_smc_remotectl_config(u32 func, u32 data) { return 0; }
+static inline int sip_smc_secure_reg_write(u32 addr_phy, u32 val) { return 0; }
+static inline u32 sip_smc_secure_reg_read(u32 addr_phy) { return 0; }
+
+static inline struct arm_smccc_res sip_smc_bus_config(u32 arg0, u32 arg1, u32 arg2)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+	return tmp;
+}
+
+static inline struct dram_addrmap_info *sip_smc_get_dram_map(void)
+{
+	return NULL;
+}
+
+static inline int sip_smc_amp_config(u32 sub_func_id,
+				     u32 arg1,
+				     u32 arg2,
+				     u32 arg3)
+{
+	return 0;
+}
+
+static inline struct arm_smccc_res sip_smc_get_amp_info(u32 sub_func_id,
+							u32 arg1)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED, };
+
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_get_pvtpll_info(u32 sub_func_id,
+							   u32 arg1)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED, };
+
+	return tmp;
+}
+
+static inline struct arm_smccc_res sip_smc_pvtpll_config(u32 sub_func_id,
+							 u32 arg1, u32 arg2,
+							 u32 arg3, u32 arg4,
+							 u32 arg5, u32 arg6)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED, };
+
+	return tmp;
+}
+
+static inline void __iomem *sip_hdcp_request_share_memory(int id)
+{
+	return NULL;
+}
+
+static inline struct arm_smccc_res sip_hdcp_config(u32 arg0, u32 arg1, u32 arg2)
+{
+	struct arm_smccc_res tmp = { .a0 = SIP_RET_NOT_SUPPORTED };
+
+	return tmp;
+}
+
+static inline ulong sip_cpu_logical_map_mpidr(u32 cpu) { return 0; }
+
+/***************************fiq debugger **************************************/
+static inline void sip_fiq_debugger_enable_fiq
+			(bool enable, uint32_t tgt_cpu) { return; }
+
+static inline void sip_fiq_debugger_enable_debug(bool enable) { return; }
+static inline int sip_fiq_debugger_uart_irq_tf_init(u32 irq_id,
+						    sip_fiq_debugger_uart_irq_tf_cb_t callback_fn)
+{
+	return 0;
+}
+
+static inline int sip_fiq_debugger_set_print_port(u32 port_phyaddr,
+						  u32 baudrate)
+{
+	return 0;
+}
+
+static inline int sip_fiq_debugger_request_share_memory(void) { return 0; }
+static inline int sip_fiq_debugger_get_target_cpu(void) { return 0; }
+static inline int sip_fiq_debugger_switch_cpu(u32 cpu) { return 0; }
+static inline int sip_fiq_debugger_sdei_switch_cpu(u32 cur_cpu, u32 target_cpu,
+						   u32 flag) { return 0; }
+static inline int sip_fiq_debugger_is_enabled(void) { return 0; }
+static inline int sip_fiq_debugger_sdei_get_event_id(u32 *fiq, u32 *sw_cpu, u32 *flag)
+{
+	return SIP_RET_NOT_SUPPORTED;
+}
+
+static inline int sip_fiq_control(u32 sub_func, u32 irq, unsigned long data)
+{
+	return 0;
+}
+
+static inline int sip_wdt_config(u32 sub_func,
+				 u32 arg1,
+				 u32 arg2,
+				 u32 arg3)
+{
+	return 0;
+}
+
+static inline int sip_hdmirx_config(u32 sub_func,
+				    u32 arg1,
+				    u32 arg2,
+				    u32 arg3)
+{
+	return SIP_RET_NOT_SUPPORTED;
+}
+
+static inline int sip_hdcpkey_init(u32 hdcp_id)
+{
+	return 0;
+}
+
+static inline int sip_smc_mcu_config(unsigned long mcu_id,
+				     unsigned long func,
+				     unsigned long arg2)
+{
+	return SIP_RET_NOT_SUPPORTED;
+}
+#endif
+
+/* 32-bit OP-TEE context, never change order of members! */
+struct sm_nsec_ctx {
+	u32 usr_sp;
+	u32 usr_lr;
+	u32 irq_spsr;
+	u32 irq_sp;
+	u32 irq_lr;
+	u32 fiq_spsr;
+	u32 fiq_sp;
+	u32 fiq_lr;
+	u32 svc_spsr;
+	u32 svc_sp;
+	u32 svc_lr;
+	u32 abt_spsr;
+	u32 abt_sp;
+	u32 abt_lr;
+	u32 und_spsr;
+	u32 und_sp;
+	u32 und_lr;
+	u32 mon_lr;
+	u32 mon_spsr;
+	u32 r4;
+	u32 r5;
+	u32 r6;
+	u32 r7;
+	u32 r8;
+	u32 r9;
+	u32 r10;
+	u32 r11;
+	u32 r12;
+	u32 r0;
+	u32 r1;
+	u32 r2;
+	u32 r3;
+};
+
+/* 64-bit ATF context, never change order of members! */
+struct gp_regs_ctx {
+	u64 x0;
+	u64 x1;
+	u64 x2;
+	u64 x3;
+	u64 x4;
+	u64 x5;
+	u64 x6;
+	u64 x7;
+	u64 x8;
+	u64 x9;
+	u64 x10;
+	u64 x11;
+	u64 x12;
+	u64 x13;
+	u64 x14;
+	u64 x15;
+	u64 x16;
+	u64 x17;
+	u64 x18;
+	u64 x19;
+	u64 x20;
+	u64 x21;
+	u64 x22;
+	u64 x23;
+	u64 x24;
+	u64 x25;
+	u64 x26;
+	u64 x27;
+	u64 x28;
+	u64 x29;
+	u64 lr;
+	u64 sp_el0;
+	u64 scr_el3;
+	u64 runtime_sp;
+	u64 spsr_el3;
+	u64 elr_el3;
+};
+
+#endif

target/linux/rockchip/files/include/linux/soc/rockchip/pvtm.h

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_ROCKCHIP_PVTM_H
+#define __SOC_ROCKCHIP_PVTM_H
+
+#if IS_ENABLED(CONFIG_ROCKCHIP_PVTM)
+u32 rockchip_get_pvtm_value(unsigned int id, unsigned int ring_sel,
+			    unsigned int time_us);
+#else
+static inline u32 rockchip_get_pvtm_value(unsigned int id,
+					  unsigned int ring_sel,
+					  unsigned int time_us)
+{
+	return 0;
+}
+#endif
+
+#endif /* __SOC_ROCKCHIP_PVTM_H */

target/linux/rockchip/files/include/soc/rockchip/rockchip_opp_select.h

@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __SOC_ROCKCHIP_OPP_SELECT_H
+#define __SOC_ROCKCHIP_OPP_SELECT_H
+
+#include <linux/pm_opp.h>
+
+#define VOLT_RM_TABLE_END	~1
+
+/*
+ * [0]:      set intermediate rate
+ *           [1]: scaling up rate or scaling down rate
+ * [1]:      add length for pvtpll
+ *           [2:5]: length
+ * [2]:      use low length for pvtpll
+ * [3:5]:    reserved
+ */
+#define OPP_RATE_MASK		0x3f
+
+/* Set intermediate rate */
+#define OPP_INTERMEDIATE_RATE	BIT(0)
+#define OPP_SCALING_UP_RATE	BIT(1)
+#define OPP_SCALING_UP_INTER	(OPP_INTERMEDIATE_RATE | OPP_SCALING_UP_RATE)
+#define OPP_SCALING_DOWN_INTER	OPP_INTERMEDIATE_RATE
+
+/* Add length for pvtpll */
+#define OPP_ADD_LENGTH		BIT(1)
+#define OPP_LENGTH_MASK		0xf
+#define OPP_LENGTH_SHIFT	2
+
+/* Use low length for pvtpll */
+#define OPP_LENGTH_LOW		BIT(2)
+
+struct rockchip_opp_info;
+
+struct volt_rm_table {
+	int volt;
+	int rm;
+};
+
+struct rockchip_opp_data {
+	config_clks_t config_clks;
+	config_regulators_t config_regulators;
+
+	int (*get_soc_info)(struct device *dev, struct device_node *np,
+			    int *bin, int *process);
+	int (*set_soc_info)(struct device *dev, struct device_node *np,
+			    struct rockchip_opp_info *info);
+	int (*set_read_margin)(struct device *dev,
+			       struct rockchip_opp_info *info,
+			       u32 rm);
+};
+
+struct pvtpll_opp_table {
+	unsigned long rate;
+	unsigned long u_volt;
+	unsigned long u_volt_min;
+	unsigned long u_volt_max;
+	unsigned long u_volt_mem;
+	unsigned long u_volt_mem_min;
+	unsigned long u_volt_mem_max;
+};
+
+/**
+ * struct rockchip_opp_info - Rockchip opp info structure
+ * @dev:		The device.
+ * @dvfs_mutex:		Mutex to protect changing volage and scmi clock rate.
+ * @data:		Device-specific opp data.
+ * @opp_table:		Temporary opp table only used when enable pvtpll calibration.
+ * @pvtpll_avg_offset:	Register offset of pvtm value.
+ * @pvtpll_min_rate:	Minimum frequency which needs calibration.
+ * @pvtpll_volt_step:	Voltage step of pvtpll calibration.
+ * @volt_rm_tbl:	Pointer to voltage to memory read margin conversion table.
+ * @grf:		General Register Files regmap.
+ * @dsu_grf:		DSU General Register Files regmap.
+ * @cci_grf:		CCI General Register Files regmap.
+ * @clocks:		Pvtpll clocks.
+ * @nclocks:		Number of pvtpll clock.
+ * @intermediate_threshold_freq: The frequency threshold of intermediate rate.
+ * @low_rm:		The read margin threshold of intermediate rate.
+ * @current_rm:		Current memory read margin.
+ * @target_rm:		Target memory read margin.
+ * @is_runtime_active:	Marks if device's pd is power on.
+ * @opp_token:		Integer replacement for opp_table.
+ * @scale:		Frequency scale.
+ * @bin:		Soc version.
+ * @process:		Process version.
+ * @volt_sel:		Speed grade.
+ * @supported_hw:	Array of version number to support.
+ * @clk:		Device's clock handle.
+ * @is_scmi_clk:	Marks if device's clock is scmi clock.
+ * @regulators:		Supply regulators.
+ * @regulator_count:	Number of power supply regulators.
+ * @init_freq:		Set the initial frequency when init opp table.
+ * @is_rate_volt_checked: Marks if device has checked initial rate and voltage.
+ * @pvtpll_clk_id:      Device's clock id.
+ * @pvtpll_low_temp:    Marks if device has low temperature pvtpll config.
+ */
+struct rockchip_opp_info {
+	struct device *dev;
+	struct mutex dvfs_mutex;
+	const struct rockchip_opp_data *data;
+	struct pvtpll_opp_table *opp_table;
+	struct regmap *pvtpll_base;
+	unsigned int pvtpll_avg_offset;
+	unsigned int pvtpll_min_rate;
+	unsigned int pvtpll_volt_step;
+
+	struct volt_rm_table *volt_rm_tbl;
+	struct regmap *grf;
+	union {
+		struct regmap *dsu_grf;
+		struct regmap *cci_grf;
+	};
+	struct clk_bulk_data *clocks;
+	int nclocks;
+	unsigned long intermediate_threshold_freq;
+	u32 low_rm;
+	u32 current_rm;
+	u32 target_rm;
+	bool is_runtime_active;
+
+	int opp_token;
+	int scale;
+	int bin;
+	int process;
+	int volt_sel;
+	u32 supported_hw[2];
+
+	struct clk *clk;
+	bool is_scmi_clk;
+	struct regulator **regulators;
+	int regulator_count;
+	unsigned int init_freq;
+	bool is_rate_volt_checked;
+
+	u32 pvtpll_clk_id;
+	bool pvtpll_low_temp;
+};
+
+#if IS_ENABLED(CONFIG_ROCKCHIP_OPP)
+int rockchip_of_get_leakage(struct device *dev, char *lkg_name, int *leakage);
+int rockchip_nvmem_cell_read_u8(struct device_node *np, const char *cell_id,
+				u8 *val);
+int rockchip_nvmem_cell_read_u16(struct device_node *np, const char *cell_id,
+				 u16 *val);
+void rockchip_get_opp_data(const struct of_device_id *matches,
+			   struct rockchip_opp_info *info);
+void rockchip_opp_dvfs_lock(struct rockchip_opp_info *info);
+void rockchip_opp_dvfs_unlock(struct rockchip_opp_info *info);
+int rockchip_init_opp_info(struct device *dev, struct rockchip_opp_info *info,
+			   char *clk_name, char *reg_name);
+void rockchip_uninit_opp_info(struct device *dev, struct rockchip_opp_info *info);
+int rockchip_adjust_opp_table(struct device *dev, struct rockchip_opp_info *info);
+int rockchip_get_read_margin(struct device *dev,
+			     struct rockchip_opp_info *info,
+			     unsigned long volt, u32 *target_rm);
+int rockchip_set_read_margin(struct device *dev,
+			     struct rockchip_opp_info *info, u32 rm,
+			     bool is_set_rm);
+int rockchip_set_intermediate_rate(struct device *dev,
+				   struct rockchip_opp_info *info,
+				   struct clk *clk, unsigned long old_freq,
+				   unsigned long new_freq, bool is_scaling_up,
+				   bool is_set_clk);
+int rockchip_opp_config_regulators(struct device *dev,
+				     struct dev_pm_opp *old_opp,
+				     struct dev_pm_opp *new_opp,
+				     struct regulator **regulators,
+				     unsigned int count,
+				     struct rockchip_opp_info *info);
+int rockchip_opp_config_clks(struct device *dev, struct opp_table *opp_table,
+			     struct dev_pm_opp *opp, void *data,
+			     bool scaling_down, struct rockchip_opp_info *info);
+int rockchip_opp_check_rate_volt(struct device *dev, struct rockchip_opp_info *info);
+int rockchip_init_opp_table(struct device *dev, struct rockchip_opp_info *info,
+			    char *clk_name, char *reg_name);
+void rockchip_uninit_opp_table(struct device *dev,
+			       struct rockchip_opp_info *info);
+#else
+static inline int rockchip_of_get_leakage(struct device *dev, char *lkg_name,
+					  int *leakage)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int rockchip_nvmem_cell_read_u8(struct device_node *np,
+					      const char *cell_id, u8 *val)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int rockchip_nvmem_cell_read_u16(struct device_node *np,
+					       const char *cell_id, u16 *val)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline void rockchip_get_opp_data(const struct of_device_id *matches,
+					 struct rockchip_opp_info *info)
+{
+}
+
+static inline void rockchip_opp_dvfs_lock(struct rockchip_opp_info *info)
+{
+}
+
+static inline void rockchip_opp_dvfs_unlock(struct rockchip_opp_info *info)
+{
+}
+
+static inline int
+rockchip_init_opp_info(struct device *dev, struct rockchip_opp_info *info,
+		       char *clk_name, char *reg_name)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline void
+rockchip_uninit_opp_info(struct device *dev, struct rockchip_opp_info *info)
+{
+}
+
+static inline int
+rockchip_adjust_opp_table(struct device *dev, struct rockchip_opp_info *info)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int rockchip_get_read_margin(struct device *dev,
+					   struct rockchip_opp_info *info,
+					   unsigned long volt, u32 *target_rm)
+{
+	return -EOPNOTSUPP;
+}
+static inline int rockchip_set_read_margin(struct device *dev,
+					   struct rockchip_opp_info *info,
+					   u32 rm, bool is_set_rm)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int
+rockchip_set_intermediate_rate(struct device *dev,
+			       struct rockchip_opp_info *opp_info,
+			       struct clk *clk, unsigned long old_freq,
+			       unsigned long new_freq, bool is_scaling_up,
+			       bool is_set_clk)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int
+rockchip_opp_config_regulators(struct device *dev,
+			       struct dev_pm_opp *old_opp,
+			       struct dev_pm_opp *new_opp,
+			       struct regulator **regulators,
+			       unsigned int count,
+			       struct rockchip_opp_info *info)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int rockchip_opp_config_clks(struct device *dev,
+					   struct opp_table *opp_table,
+					   struct dev_pm_opp *opp, void *data,
+					   bool scaling_down,
+					   struct rockchip_opp_info *info)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int rockchip_opp_check_rate_volt(struct device *dev,
+					       struct rockchip_opp_info *info)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline int
+rockchip_init_opp_table(struct device *dev, struct rockchip_opp_info *info,
+			char *clk_name, char *reg_name)
+{
+	return -EOPNOTSUPP;
+}
+
+static inline void rockchip_uninit_opp_table(struct device *dev,
+					     struct rockchip_opp_info *info)
+{
+}
+
+#endif /* CONFIG_ROCKCHIP_OPP */
+
+#endif

target/linux/rockchip/patches-6.6/810-rockchip-clk-api.patch

@@ -0,0 +1,234 @@
+From 9ebada0adea894db97a9460180860e45ca4d2f78 Mon Sep 17 00:00:00 2001
+From: jjm2473 <jjm2473@gmail.com>
+Date: Fri, 21 Mar 2025 16:31:21 +0800
+Subject: [PATCH] rockchip/clk: add rockchip_pll_clk api
+
+---
+ drivers/clk/rockchip/clk-pll.c | 110 +++++++++++++++++++++++++++++++--
+ drivers/clk/rockchip/clk.h     |   3 +
+ 2 files changed, 109 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
+index 2d42eb628..5b01660cb 100644
+--- a/drivers/clk/rockchip/clk-pll.c
++++ b/drivers/clk/rockchip/clk-pll.c
+@@ -38,6 +38,8 @@ struct rockchip_clk_pll {
+ 	u8			flags;
+ 	const struct rockchip_pll_rate_table *rate_table;
+ 	unsigned int		rate_count;
++	int			sel;
++	unsigned long		scaling;
+ 	spinlock_t		*lock;
+ 
+ 	struct rockchip_clk_provider *ctx;
+@@ -47,6 +49,72 @@ struct rockchip_clk_pll {
+ #define to_rockchip_clk_pll_nb(nb) \
+ 			container_of(nb, struct rockchip_clk_pll, clk_nb)
+ 
++int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel)
++{
++	struct clk *parent = clk_get_parent(clk);
++	struct rockchip_clk_pll *pll;
++
++	if (IS_ERR_OR_NULL(parent))
++		return -EINVAL;
++
++	pll = to_rockchip_clk_pll(__clk_get_hw(parent));
++	if (!pll)
++		return -EINVAL;
++
++	pll->sel = sel;
++
++	return 0;
++}
++EXPORT_SYMBOL(rockchip_pll_clk_adaptive_scaling);
++
++int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate)
++{
++	const struct rockchip_pll_rate_table *rate_table;
++	struct clk *parent = clk_get_parent(clk);
++	struct rockchip_clk_pll *pll;
++	unsigned int i;
++
++	if (IS_ERR_OR_NULL(parent))
++		return -EINVAL;
++
++	pll = to_rockchip_clk_pll(__clk_get_hw(parent));
++	if (!pll)
++		return -EINVAL;
++
++	rate_table = pll->rate_table;
++	for (i = 0; i < pll->rate_count; i++) {
++		if (rate >= rate_table[i].rate)
++			return i;
++	}
++
++	return -EINVAL;
++}
++EXPORT_SYMBOL(rockchip_pll_clk_rate_to_scale);
++
++int rockchip_pll_clk_scale_to_rate(struct clk *clk, unsigned int scale)
++{
++	const struct rockchip_pll_rate_table *rate_table;
++	struct clk *parent = clk_get_parent(clk);
++	struct rockchip_clk_pll *pll;
++	unsigned int i;
++
++	if (IS_ERR_OR_NULL(parent))
++		return -EINVAL;
++
++	pll = to_rockchip_clk_pll(__clk_get_hw(parent));
++	if (!pll)
++		return -EINVAL;
++
++	rate_table = pll->rate_table;
++	for (i = 0; i < pll->rate_count; i++) {
++		if (i == scale)
++			return rate_table[i].rate;
++	}
++
++	return -EINVAL;
++}
++EXPORT_SYMBOL(rockchip_pll_clk_scale_to_rate);
++
+ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
+ 			    struct rockchip_clk_pll *pll, unsigned long rate)
+ {
+@@ -54,9 +122,16 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
+ 	int i;
+ 
+ 	for (i = 0; i < pll->rate_count; i++) {
+-		if (rate == rate_table[i].rate)
++		if (rate == rate_table[i].rate) {
++			if (i < pll->sel) {
++				pll->scaling = rate;
++				return &rate_table[pll->sel];
++			}
++			pll->scaling = 0;
+ 			return &rate_table[i];
++		}
+ 	}
++	pll->scaling = 0;
+ 
+ 	return NULL;
+ }
+@@ -167,6 +242,9 @@ static unsigned long rockchip_rk3036_pll_recalc_rate(struct clk_hw *hw,
+ 	struct rockchip_pll_rate_table cur;
+ 	u64 rate64 = prate;
+ 
++	if (pll->sel && pll->scaling)
++		return pll->scaling;
++
+ 	rockchip_rk3036_pll_get_params(pll, &cur);
+ 
+ 	rate64 *= cur.fbdiv;
+@@ -412,6 +490,9 @@ static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
+ 		return prate;
+ 	}
+ 
++	if (pll->sel && pll->scaling)
++		return pll->scaling;
++
+ 	rockchip_rk3066_pll_get_params(pll, &cur);
+ 
+ 	rate64 *= cur.nf;
+@@ -485,6 +566,7 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ {
+ 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ 	const struct rockchip_pll_rate_table *rate;
++	int ret;
+ 
+ 	pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
+ 		 __func__, clk_hw_get_name(hw), drate, prate);
+@@ -497,7 +579,11 @@ static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ 		return -EINVAL;
+ 	}
+ 
+-	return rockchip_rk3066_pll_set_params(pll, rate);
++	ret = rockchip_rk3066_pll_set_params(pll, rate);
++	if (ret)
++		pll->scaling = 0;
++
++	return ret;
+ }
+ 
+ static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
+@@ -649,6 +735,9 @@ static unsigned long rockchip_rk3399_pll_recalc_rate(struct clk_hw *hw,
+ 	struct rockchip_pll_rate_table cur;
+ 	u64 rate64 = prate;
+ 
++	if (pll->sel && pll->scaling)
++		return pll->scaling;
++
+ 	rockchip_rk3399_pll_get_params(pll, &cur);
+ 
+ 	rate64 *= cur.fbdiv;
+@@ -734,6 +823,7 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ {
+ 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ 	const struct rockchip_pll_rate_table *rate;
++	int ret;
+ 
+ 	pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
+ 		 __func__, __clk_get_name(hw->clk), drate, prate);
+@@ -746,7 +836,11 @@ static int rockchip_rk3399_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ 		return -EINVAL;
+ 	}
+ 
+-	return rockchip_rk3399_pll_set_params(pll, rate);
++	ret = rockchip_rk3399_pll_set_params(pll, rate);
++	if (ret)
++		pll->scaling = 0;
++
++	return ret;
+ }
+ 
+ static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
+@@ -899,6 +993,9 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned
+ 	struct rockchip_pll_rate_table cur;
+ 	u64 rate64 = prate, postdiv;
+ 
++	if (pll->sel && pll->scaling)
++		return pll->scaling;
++
+ 	rockchip_rk3588_pll_get_params(pll, &cur);
+ 
+ 	rate64 *= cur.m;
+@@ -980,6 +1077,7 @@ static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ {
+ 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+ 	const struct rockchip_pll_rate_table *rate;
++	int ret;
+ 
+ 	pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
+ 		 __func__, __clk_get_name(hw->clk), drate, prate);
+@@ -992,7 +1090,11 @@ static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate,
+ 		return -EINVAL;
+ 	}
+ 
+-	return rockchip_rk3588_pll_set_params(pll, rate);
++	ret = rockchip_rk3588_pll_set_params(pll, rate);
++	if (ret)
++		pll->scaling = 0;
++
++	return ret;
+ }
+ 
+ static int rockchip_rk3588_pll_enable(struct clk_hw *hw)
+diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
+index fd3b476de..1bcfc39fb 100644
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -987,6 +987,9 @@ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ 			const struct rockchip_cpuclk_reg_data *reg_data,
+ 			const struct rockchip_cpuclk_rate_table *rates,
+ 			int nrates);
++int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate);
++int rockchip_pll_clk_scale_to_rate(struct clk *clk, unsigned int scale);
++int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel);
+ void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
+ void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
+ 					unsigned int reg, void (*cb)(void));
+-- 
+2.46.0
+

target/linux/rockchip/patches-6.6/811-drivers-add-rockchip-opp.patch

@@ -0,0 +1,37 @@
+From 2e7f97d4228b45b6be6895490b9bbeb67a952c14 Mon Sep 17 00:00:00 2001
+From: jjm2473 <jjm2473@gmail.com>
+Date: Fri, 21 Mar 2025 18:09:43 +0800
+Subject: [PATCH] drivers: add rockchip opp
+
+---
+ drivers/soc/rockchip/Kconfig  | 6 ++++++
+ drivers/soc/rockchip/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig
+index aff2f7e95..4ec085435 100644
+--- a/drivers/soc/rockchip/Kconfig
++++ b/drivers/soc/rockchip/Kconfig
+@@ -42,4 +42,10 @@ config ROCKCHIP_DTPM
+ 	  on this platform. That will create all the power capping capable
+ 	  devices.
+ 
++config ROCKCHIP_OPP
++	tristate "Rockchip OPP select support"
++	depends on PM_DEVFREQ
++	help
++	  Say y here to enable rockchip OPP support.
++
+ endif
+diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile
+index 23d414433..7fa6f324d 100644
+--- a/drivers/soc/rockchip/Makefile
++++ b/drivers/soc/rockchip/Makefile
+@@ -5,3 +5,4 @@
+ obj-$(CONFIG_ROCKCHIP_GRF) += grf.o
+ obj-$(CONFIG_ROCKCHIP_IODOMAIN) += io-domain.o
+ obj-$(CONFIG_ROCKCHIP_DTPM) += dtpm.o
++obj-$(CONFIG_ROCKCHIP_OPP) += rockchip_opp_select.o
+-- 
+2.46.0
+

target/linux/rockchip/patches-6.6/812-drivers-add-rockchip-pvtm.patch

@@ -0,0 +1,39 @@
+From ea097df4006ad966e37db6205dc97346e1432748 Mon Sep 17 00:00:00 2001
+From: jjm2473 <jjm2473@gmail.com>
+Date: Fri, 21 Mar 2025 18:10:15 +0800
+Subject: [PATCH] drivers: add rockchip pvtm
+
+---
+ drivers/soc/rockchip/Kconfig  | 8 ++++++++
+ drivers/soc/rockchip/Makefile | 1 +
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/soc/rockchip/Kconfig b/drivers/soc/rockchip/Kconfig
+index 4ec085435..152f241f2 100644
+--- a/drivers/soc/rockchip/Kconfig
++++ b/drivers/soc/rockchip/Kconfig
+@@ -48,4 +48,12 @@ config ROCKCHIP_OPP
+ 	help
+ 	  Say y here to enable rockchip OPP support.
+ 
++config ROCKCHIP_PVTM
++	tristate "Rockchip PVTM support"
++	help
++	  Say y here to enable pvtm support.
++	  The Process-Voltage-Temperature Monitor (PVTM) is used to monitor
++	  the chip performance variance caused by chip process, voltage and
++	  temperature.
++
+ endif
+diff --git a/drivers/soc/rockchip/Makefile b/drivers/soc/rockchip/Makefile
+index 7fa6f324d..c1340db95 100644
+--- a/drivers/soc/rockchip/Makefile
++++ b/drivers/soc/rockchip/Makefile
+@@ -6,3 +6,4 @@ obj-$(CONFIG_ROCKCHIP_GRF) += grf.o
+ obj-$(CONFIG_ROCKCHIP_IODOMAIN) += io-domain.o
+ obj-$(CONFIG_ROCKCHIP_DTPM) += dtpm.o
+ obj-$(CONFIG_ROCKCHIP_OPP) += rockchip_opp_select.o
++obj-$(CONFIG_ROCKCHIP_PVTM) += rockchip_pvtm.o
+-- 
+2.46.0
+