From 99075b24e3df54a737bd81fd06cfe9a3534e3e3a Mon Sep 17 00:00:00 2001 From: Liangbin Lian Date: Wed, 9 Apr 2025 14:57:22 +0800 Subject: [PATCH] target/rockchip: add hinlink rk3568 series --- .../armv8/base-files/etc/board.d/01_leds | 10 + .../armv8/base-files/etc/board.d/02_network | 5 + .../armv8/base-files/lib/preinit/04_board | 43 ++ .../linux/rockchip/dts/rk3568/rk3568-ars4.dts | 8 + .../rockchip/dts/rk3568/rk3568-hinlink.dtsi | 602 ++++++++++++++++++ .../linux/rockchip/dts/rk3568/rk3568-hnas.dts | 249 ++++++++ .../rockchip/dts/rk3568/rk3568-opc-h66k.dts | 30 + .../rockchip/dts/rk3568/rk3568-opc-h68k.dts | 102 +++ .../rockchip/dts/rk3568/rk3568-opc-h69k.dts | 169 +++++ target/linux/rockchip/image/legacy.mk | 30 + .../image/legacy/rk3568-hinlink.bootscript | 50 ++ 11 files changed, 1298 insertions(+) create mode 100644 target/linux/rockchip/armv8/base-files/lib/preinit/04_board create mode 100644 target/linux/rockchip/dts/rk3568/rk3568-ars4.dts create mode 100644 target/linux/rockchip/dts/rk3568/rk3568-hinlink.dtsi create mode 100644 target/linux/rockchip/dts/rk3568/rk3568-hnas.dts create mode 100644 target/linux/rockchip/dts/rk3568/rk3568-opc-h66k.dts create mode 100644 target/linux/rockchip/dts/rk3568/rk3568-opc-h68k.dts create mode 100644 target/linux/rockchip/dts/rk3568/rk3568-opc-h69k.dts create mode 100644 target/linux/rockchip/image/legacy/rk3568-hinlink.bootscript diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds index c7c9f1da2b..cf6912ead7 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds @@ -35,6 +35,16 @@ friendlyarm,nanopi-r6s) ucidef_set_led_netdev "lan1" "LAN1" "green:lan-1" "eth2" ucidef_set_led_netdev "lan2" "LAN2" "green:lan-2" "eth0" ;; +easepi,ars4|\ +hinlink,h88k-*|\ +hinlink,h88k|\ +hinlink,hnas|\ +hinlink,opc-h69k|\ +hinlink,opc-h68k|\ +hinlink,opc-h66k) + ucidef_set_led_netdev "wan" "WAN" "blue:net" "eth0" + ucidef_set_led_ide "disk" "DISK" "yellow:disk" + ;; esac board_config_flush diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network index 440118bb83..c1d7a2f554 100644 --- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network +++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network @@ -8,6 +8,7 @@ rockchip_setup_interfaces() case "$board" in armsom,sige7|\ + easepi,ars4|\ lunzn,fastrhino-r66s|\ friendlyarm,nanopi-r2c|\ friendlyarm,nanopi-r2c-plus|\ @@ -16,6 +17,8 @@ rockchip_setup_interfaces() friendlyarm,nanopi-r4s|\ friendlyarm,nanopi-r4s-enterprise|\ friendlyarm,nanopi-r6c|\ + hinlink,opc-h66k|\ + hinlink,hnas|\ radxa,rockpi-e|\ xunlong,orangepi-r1-plus|\ xunlong,orangepi-r1-plus-lts) @@ -28,6 +31,7 @@ rockchip_setup_interfaces() radxa,rock-3b) ucidef_set_interfaces_lan_wan 'eth0' 'eth1' ;; + hinlink,opc-h69k|\ friendlyarm,nanopi-r5s) ucidef_set_interfaces_lan_wan 'eth1 eth2' 'eth0' ;; @@ -35,6 +39,7 @@ rockchip_setup_interfaces() ucidef_set_interfaces_lan_wan 'eth0 eth2' 'eth1' ;; easepi,r1|easepi,r1-lite|\ + hinlink,opc-h68k|\ lunzn,fastrhino-r68s) ucidef_set_interfaces_lan_wan 'eth1 eth2 eth3' 'eth0' ;; diff --git a/target/linux/rockchip/armv8/base-files/lib/preinit/04_board b/target/linux/rockchip/armv8/base-files/lib/preinit/04_board new file mode 100644 index 0000000000..051009cabe --- /dev/null +++ b/target/linux/rockchip/armv8/base-files/lib/preinit/04_board @@ -0,0 +1,43 @@ + +preinit_set_gpio() { + # ref package/base-files/files/etc/init.d/gpio_switch + local gpio_pin="$1" + local value="$2" + + [ -z "$gpio_pin" ] && return 1 + + local gpio_path + if [ -n "$(echo "$gpio_pin" | grep -E "^[0-9]+$")" ]; then + gpio_path="/sys/class/gpio/gpio${gpio_pin}" + + # export GPIO pin for access + [ -d "$gpio_path" ] || { + echo "$gpio_pin" >/sys/class/gpio/export + # we need to wait a bit until the GPIO appears + [ -d "$gpio_path" ] || sleep 1 + } + + # direction attribute only exists if the kernel supports changing the + # direction of a GPIO + if [ -e "${gpio_path}/direction" ]; then + # set the pin to output with high or low pin value + { [ "$value" = "0" ] && echo "low" || echo "high"; } \ + >"$gpio_path/direction" + else + { [ "$value" = "0" ] && echo "0" || echo "1"; } \ + >"$gpio_path/value" + fi + fi +} + +preinit_gpio() { + case $(board_name) in + easepi,ars4|\ + hinlink,hnas) + # set GPIO4_A7 to high, deassert SATA PM chip + preinit_set_gpio 135 + ;; + esac +} + +boot_hook_add preinit_main preinit_gpio diff --git a/target/linux/rockchip/dts/rk3568/rk3568-ars4.dts b/target/linux/rockchip/dts/rk3568/rk3568-ars4.dts new file mode 100644 index 0000000000..1be029e850 --- /dev/null +++ b/target/linux/rockchip/dts/rk3568/rk3568-ars4.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +#include "rk3568-hnas.dts" + +/ { + model = "EasePi ARS4"; + compatible = "easepi,ars4", "rockchip,rk3568"; +}; diff --git a/target/linux/rockchip/dts/rk3568/rk3568-hinlink.dtsi b/target/linux/rockchip/dts/rk3568/rk3568-hinlink.dtsi new file mode 100644 index 0000000000..b9285e4d2a --- /dev/null +++ b/target/linux/rockchip/dts/rk3568/rk3568-hinlink.dtsi @@ -0,0 +1,602 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "rk3568-ip.dtsi" +#include "rk3568-ip-rk809.dtsi" + +/ { + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + + led-boot = &led_green; + led-failsafe = &led_green; + led-running = &led_green; + led-upgrade = &led_green; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_sys_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&reset_button>; + + button@1 { + label = "reset_button"; + linux,code = ; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = + <&led_green_en>, + <&led_yellow_en>, + <&led_blue_en>; + + led_green: green { + gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + label = "green:sys"; + linux,default-trigger = "heartbeat"; + }; + led_yellow: yellow { + gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + label = "yellow:disk"; + }; + led_blue: blue { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "blue:net"; + }; + }; + +}; + +&combphy0 { + rockchip,dis-u3otg0-port; /* disable USB3.0 */ + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + power-off-delay-ms = <200>; + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + }; +}; + +&i2c5 { + status = "okay"; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; +}; + +&pcie2x1 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + data-lanes = <1 2>; + status = "okay"; +}; + +&pcie3x1 { + num-lanes = <1>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + num-lanes = <1>; + rockchip,init-delay-ms = <100>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + + leds { + led_green_en: led-green-en { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_yellow_en: led-yellow-en { + rockchip,pins = + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_blue_en: led-blue-en { + rockchip,pins = + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + reset_button: reset-button { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc { + vcc3v3_sys_en: vcc3v3-sys-en { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */ +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "disabled"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_otg>; + status = "disabled"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; diff --git a/target/linux/rockchip/dts/rk3568/rk3568-hnas.dts b/target/linux/rockchip/dts/rk3568/rk3568-hnas.dts new file mode 100644 index 0000000000..2d8de4854a --- /dev/null +++ b/target/linux/rockchip/dts/rk3568/rk3568-hnas.dts @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* +* Copyright (c) 2020 Rockchip Electronics Co., Ltd. +*/ + +/dts-v1/; + +#include "rk3568-hinlink.dtsi" +#include + +/ { + model = "HINLINK HNAS Board"; + compatible = "hinlink,hnas", "rockchip,rk3568"; + + reg-sata-pm-pwr { + compatible = "regulator-fixed"; + regulator-name = "reg_sata_pm_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sata_pm_pwr>, <&sata_pm_reset_low>; + vin-supply = <&vcc5v0_sys>; + }; + + reg-sata-pm-reset { + compatible = "regulator-fixed"; + regulator-name = "reg_sata_pm_reset"; + regulator-always-on; + regulator-boot-on; + startup-delay-us = <12000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sata_pm_reset>; + /** + * kernel boot slow with log + * `ata1: link is slow to respond, please be patient` + * disable it now, and enable it after system startup + * + * UPDATE: above error just because CONFIG_SATA_PMP not enabled on kernel + * but we keep this disabled to avoiding scan rootfs from SATA + */ + status = "disabled"; + }; + + vcc5v0_sata0_pwr: vcc5v0-sata0-pwr { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sata0_pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_sata0_pwr_en>; + vin-supply = <&vcc5v0_sys>; + }; + + disk-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = + <&led_disk1_en>, + <&led_disk2_en>, + <&led_disk3_en>, + <&led_disk4_en>; + + led-disk1 { + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + label = "green:disk1"; + linux,default-trigger = "ata1p3"; + }; + led-disk2 { + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "green:disk2"; + linux,default-trigger = "ata1p0"; + }; + led-disk3 { + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + label = "green:disk3"; + linux,default-trigger = "ata1p2"; + }; + led-disk4 { + function = LED_FUNCTION_DISK_ACTIVITY; + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + label = "green:disk4"; + linux,default-trigger = "ata1p1"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 0x55 0x66 0x77 0x88 0x99 0xbb 0xcc 0xff>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm0 0 50000 0>; + }; +}; + +&chosen { + default-firewall = "nas"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c5 { + status = "disabled"; +}; + +&combphy0 { + // pinctrl-names = "default"; + // pinctrl-0 = <&sata_pm_reset_high>; + status = "okay"; +}; + +&sata0 { + /** + * Uncomment this line to enable FBS + */ + compatible = "rockchip,rk-ahci", "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + target-supply = <&vcc5v0_sata0_pwr>; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&usb2phy0_otg { + vbus-supply = <&vcc5v0_sys>; + rockchip,vbus-always-on; + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&cpu_thermal { + trips { + + cpu_warm: cpu_warm { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <85000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_hall: cpu_hall { + temperature = <95000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_idle: cpu_idle { + temperature = <47000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_idle>; + cooling-device = <&fan THERMAL_NO_LIMIT 2>; + }; + + map3 { + trip = <&cpu_warm>; + cooling-device = <&fan 2 4>; + }; + + map4 { + trip = <&cpu_hot>; + cooling-device = <&fan 4 6>; + }; + + map5 { + trip = <&cpu_hall>; + cooling-device = <&fan 6 THERMAL_NO_LIMIT>; + }; + + }; +}; + +&pinctrl { + sata { + sata_pm_pwr: sata-pm-pwr { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + sata_pm_reset: sata-pm-reset { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + sata_pm_reset_low: sata-pm-reset-low { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_output_low>; + }; + sata_pm_reset_high: sata-pm-reset-high { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_output_high>; + }; + vcc5v0_sata0_pwr_en: vcc5v0-sata0-pwr-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + leds { + led_disk1_en: led-disk1-en { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_disk2_en: led-disk2-en { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_disk3_en: led-disk3-en { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_disk4_en: led-disk4-en { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/target/linux/rockchip/dts/rk3568/rk3568-opc-h66k.dts b/target/linux/rockchip/dts/rk3568/rk3568-opc-h66k.dts new file mode 100644 index 0000000000..dd2bbbc9e7 --- /dev/null +++ b/target/linux/rockchip/dts/rk3568/rk3568-opc-h66k.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Flippy + */ + +/dts-v1/; + +#include "rk3568-hinlink.dtsi" + +/ { + model = "HINLINK OPC-H66K Board"; + compatible = "hinlink,opc-h66k", "rockchip,rk3568"; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&pwm0 { + status = "disabled"; +}; + +&i2c5 { + status = "disabled"; +}; diff --git a/target/linux/rockchip/dts/rk3568/rk3568-opc-h68k.dts b/target/linux/rockchip/dts/rk3568/rk3568-opc-h68k.dts new file mode 100644 index 0000000000..61ba5d3859 --- /dev/null +++ b/target/linux/rockchip/dts/rk3568/rk3568-opc-h68k.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568-hinlink.dtsi" + +/ { + model = "HINLINK OPC-H68K/H69K Board"; + compatible = "hinlink,opc-h68k", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + phy-handle = <&rgmii_phy0>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x20>; + rx_delay = <0x2f>; + + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + phy-handle = <&rgmii_phy1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pinctrl { + gmac0 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac1 { + eth_phy1_reset_pin: eth-phy1-reset-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/target/linux/rockchip/dts/rk3568/rk3568-opc-h69k.dts b/target/linux/rockchip/dts/rk3568/rk3568-opc-h69k.dts new file mode 100644 index 0000000000..4675275902 --- /dev/null +++ b/target/linux/rockchip/dts/rk3568/rk3568-opc-h69k.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568-hinlink.dtsi" + +/ { + model = "HINLINK OPC-H69K Board"; + compatible = "hinlink,opc-h69k", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac1; + }; + + vcc3v3_ssd: vcc3v3-ssd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ssd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_ssd_en>; + }; + + modem-enable-regulator { + compatible = "regulator-fixed"; + regulator-name = "modem_enable"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + startup-delay-us = <2000000>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&modem_enable_en>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 0x55 0x66 0x77 0x88 0x99 0xbb 0xcc 0xff>; + #cooling-cells = <2>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm0 0 50000 0>; + }; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 15ms, 50ms for rtl8211f */ + snps,reset-delays-us = <0 15000 50000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + phy-handle = <&rgmii_phy1>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-0 = <ð_phy1_reset_pin>; + pinctrl-names = "default"; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <65000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <85000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_hall: cpu_hall { + temperature = <95000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_idle: cpu_idle { + temperature = <20000>; + hysteresis = <3000>; + type = "passive"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_idle>; + cooling-device = <&fan THERMAL_NO_LIMIT 2>; + }; + + map3 { + trip = <&cpu_warm>; + cooling-device = <&fan 2 4>; + }; + + map4 { + trip = <&cpu_hot>; + cooling-device = <&fan 4 6>; + }; + + map5 { + trip = <&cpu_hall>; + cooling-device = <&fan 6 THERMAL_NO_LIMIT>; + }; + + }; +}; + +&pinctrl { + gmac1 { + eth_phy1_reset_pin: eth-phy1-reset-pin { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + ssd { + vcc3v3_ssd_en: vcc3v3-ssd-en { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + modem { + modem_enable_en: modem-enable-en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/target/linux/rockchip/image/legacy.mk b/target/linux/rockchip/image/legacy.mk index d205bc3f60..8a212146cf 100644 --- a/target/linux/rockchip/image/legacy.mk +++ b/target/linux/rockchip/image/legacy.mk @@ -23,6 +23,14 @@ $(call Device/Legacy/rk3568,$(1)) endef TARGET_DEVICES += easepi_r1 +define Device/easepi_ars4 +$(call Device/Legacy/rk3568,$(1)) + DEVICE_VENDOR := EasePi + DEVICE_MODEL := ARS4 + DEVICE_PACKAGES += kmod-r8169 kmod-ata-ahci-dwc kmod-hwmon-pwmfan kmod-thermal +endef +TARGET_DEVICES += easepi_ars4 + define Device/fastrhino_r6xs $(call Device/Legacy/rk3568,$(1)) DEVICE_VENDOR := FastRhino @@ -52,6 +60,28 @@ $(call Device/friendlyarm_nanopi-r5c,$(1)) endef +define Device/rk3568/hinlink +$(call Device/Legacy/rk3568,$(1)) + DEVICE_VENDOR := HINLINK + DEVICE_PACKAGES += kmod-r8169 kmod-ata-ahci-dwc kmod-hwmon-pwmfan kmod-thermal +endef + +define Device/hinlink_opc-h6xk +$(call Device/rk3568/hinlink,$(1)) + DEVICE_MODEL := OPC-H69K/H68K/H66K combined + SUPPORTED_DEVICES += hinlink,opc-h66k hinlink,opc-h68k hinlink,opc-h69k + DEVICE_DTS := rk3568/rk3568-opc-h66k rk3568/rk3568-opc-h68k rk3568/rk3568-opc-h69k + BOOT_SCRIPT := rk3568-hinlink +endef +TARGET_DEVICES += hinlink_opc-h6xk + +define Device/hinlink_hnas +$(call Device/rk3568/hinlink,$(1)) + DEVICE_MODEL := HNAS +endef +TARGET_DEVICES += hinlink_hnas + + # RK3588 define Device/Legacy/rk3588 diff --git a/target/linux/rockchip/image/legacy/rk3568-hinlink.bootscript b/target/linux/rockchip/image/legacy/rk3568-hinlink.bootscript new file mode 100644 index 0000000000..0708799e5e --- /dev/null +++ b/target/linux/rockchip/image/legacy/rk3568-hinlink.bootscript @@ -0,0 +1,50 @@ +# hinlink rk3568 combined image + +env delete hwflag +env delete adc_value + +# using gpio 143 (GPIO4_B7, GMAC1_MDIO_M1) to detect gmac1 +if gpio input 143; then + echo nogmac +else + echo hasgmac1 + setenv hwflag 1 + + # using SARADC CH7 to detect hwrev + adc single saradc@fe720000 7 adc_value + + if test -n "$adc_value"; then + # h68k 511-524 + # h69k 691-695 + if test "$adc_value" -ge 1024; then + if test "$adc_value" -ge 1072265; then + echo h69k + setenv hwflag 10 + fi + elif test "$adc_value" -ge 610; then + echo h69k + setenv hwflag 10 + fi + fi +fi + +if test "$hwflag" = "10" ; then + # reset USB modem + # 1. set RESET(GPIO0_C0) to high, will invert to low on module RESET# + gpio set 16 + # 2. pull down USB power GPIO0_A5 + # gpio clear 5 +fi + +env delete adc_value + +part uuid mmc ${devnum}:2 uuid + +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait" + +load mmc ${devnum}:1 ${fdt_addr_r} rockchip${hwflag}.dtb +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img + +env delete hwflag + +booti ${kernel_addr_r} - ${fdt_addr_r} \ No newline at end of file