target/rockchip: add YT85xx driver for r2c
https://github.com/immortalwrt/immortalwrt/tree/openwrt-21.02/target/linux/rockchip
This commit is contained in:
jjm2473
parent
85a4b8fcbc
commit
9a525eacc2
@ -266,6 +266,7 @@ CONFIG_MMC_SDHCI_OF_ARASAN=y
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CONFIG_MMC_SDHCI_OF_DWCMSHC=y
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# CONFIG_MMC_SDHCI_PCI is not set
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CONFIG_MMC_SDHCI_PLTFM=y
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CONFIG_MOTORCOMM_PHY=y
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CONFIG_MQ_IOSCHED_DEADLINE=y
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# CONFIG_MTD_CFI is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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414
target/linux/rockchip/files/drivers/net/phy/motorcomm.c
Normal file
414
target/linux/rockchip/files/drivers/net/phy/motorcomm.c
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@ -0,0 +1,414 @@
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/*
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* drivers/net/phy/motorcomm.c
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*
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* Driver for Motorcomm PHYs
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*
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* Author: Leilei Zhao <leilei.zhao@motorcomm.com>
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*
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* Copyright (c) 2019 Motorcomm, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Support : Motorcomm Phys:
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* Giga phys: yt8511, yt8521
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* 100/10 Phys : yt8512, yt8512b, yt8510
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* Automotive 100Mb Phys : yt8010
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* Automotive 100/10 hyper range Phys: yt8510
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/motorcomm_phy.h>
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#include <linux/of.h>
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#include <linux/clk.h>
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static int ytphy_read_ext(struct phy_device *phydev, u32 regnum)
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{
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int ret;
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int val;
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ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
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if (ret < 0)
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return ret;
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val = phy_read(phydev, REG_DEBUG_DATA);
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return val;
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}
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static int ytphy_write_ext(struct phy_device *phydev, u32 regnum, u16 val)
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{
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int ret;
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ret = phy_write(phydev, REG_DEBUG_ADDR_OFFSET, regnum);
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if (ret < 0)
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return ret;
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ret = phy_write(phydev, REG_DEBUG_DATA, val);
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return ret;
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}
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static int yt8010_config_aneg(struct phy_device *phydev)
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{
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phydev->speed = SPEED_100;
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return 0;
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}
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static int yt8511_config_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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/* disable auto sleep */
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val = ytphy_read_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1);
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if (val < 0)
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return val;
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val &= (~BIT(YT8511_EN_SLEEP_SW_BIT));
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ret = ytphy_write_ext(phydev, YT8511_EXTREG_SLEEP_CONTROL1, val);
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if (ret < 0)
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return ret;
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/* output SyncE clock (125mhz) even link is down */
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ret = ytphy_write_ext(phydev, 0xa012, 0xd0);
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if (ret < 0)
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return ret;
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/* enable RXC clock when no wire plug */
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val = ytphy_read_ext(phydev, 0xc);
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if (val < 0)
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return val;
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/* ext reg 0xc.b[2:1]
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00-----25M from pll;
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01---- 25M from xtl;(default)
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10-----62.5M from pll;
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11----125M from pll(here set to this value)
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*/
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val |= (3 << 1);
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ret = ytphy_write_ext(phydev, 0xc, val);
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if (ret < 0)
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return ret;
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/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
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ytphy_write_ext(phydev, 0xa00b, 0xe004);
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ytphy_write_ext(phydev, 0xa00c, 0);
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ytphy_write_ext(phydev, 0xa00d, 0x2600);
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ytphy_write_ext(phydev, 0xa00e, 0x0070);
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ytphy_write_ext(phydev, 0xa00f, 0x000a);
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return 0;
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}
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static int yt8512_clk_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_AFE_PLL);
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if (val < 0)
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return val;
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val |= YT8512_CONFIG_PLL_REFCLK_SEL_EN;
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_AFE_PLL, val);
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if (ret < 0)
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return ret;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_EXTEND_COMBO);
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if (val < 0)
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return val;
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val |= YT8512_CONTROL1_RMII_EN;
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_EXTEND_COMBO, val);
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if (ret < 0)
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return ret;
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val = phy_read(phydev, MII_BMCR);
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if (val < 0)
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return val;
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val |= YT_SOFTWARE_RESET;
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ret = phy_write(phydev, MII_BMCR, val);
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return ret;
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}
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static int yt8512_led_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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int mask;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_LED0);
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if (val < 0)
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return val;
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val |= YT8512_LED0_ACT_BLK_IND;
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mask = YT8512_LED0_DIS_LED_AN_TRY | YT8512_LED0_BT_BLK_EN |
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YT8512_LED0_HT_BLK_EN | YT8512_LED0_COL_BLK_EN |
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YT8512_LED0_BT_ON_EN;
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val &= ~mask;
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_LED0, val);
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if (ret < 0)
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return ret;
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val = ytphy_read_ext(phydev, YT8512_EXTREG_LED1);
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if (val < 0)
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return val;
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val |= YT8512_LED1_BT_ON_EN;
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mask = YT8512_LED1_TXACT_BLK_EN | YT8512_LED1_RXACT_BLK_EN;
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val &= ~mask;
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ret = ytphy_write_ext(phydev, YT8512_LED1_BT_ON_EN, val);
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return ret;
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}
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static int yt8512_config_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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ret = yt8512_clk_init(phydev);
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if (ret < 0)
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return ret;
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ret = yt8512_led_init(phydev);
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/* disable auto sleep */
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val = ytphy_read_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1);
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if (val < 0)
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return val;
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val &= (~BIT(YT8512_EN_SLEEP_SW_BIT));
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ret = ytphy_write_ext(phydev, YT8512_EXTREG_SLEEP_CONTROL1, val);
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if (ret < 0)
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return ret;
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return ret;
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}
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static int yt8512_read_status(struct phy_device *phydev)
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{
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int ret;
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int val;
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int speed, speed_mode, duplex;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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val = phy_read(phydev, REG_PHY_SPEC_STATUS);
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if (val < 0)
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return val;
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duplex = (val & YT8512_DUPLEX) >> YT8512_DUPLEX_BIT;
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speed_mode = (val & YT8512_SPEED_MODE) >> YT8512_SPEED_MODE_BIT;
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switch (speed_mode) {
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case 0:
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speed = SPEED_10;
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break;
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case 1:
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speed = SPEED_100;
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break;
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case 2:
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case 3:
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default:
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speed = SPEED_UNKNOWN;
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break;
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}
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phydev->speed = speed;
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phydev->duplex = duplex;
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return 0;
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}
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static int yt8521_config_init(struct phy_device *phydev)
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{
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int ret;
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int val;
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/* disable auto sleep */
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val = ytphy_read_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1);
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if (val < 0)
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return val;
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val &= (~BIT(YT8521_EN_SLEEP_SW_BIT));
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ret = ytphy_write_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1, val);
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if (ret < 0)
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return ret;
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/* switch to access UTP */
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ret = ytphy_write_ext(phydev, 0xa000, 0);
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if (ret < 0)
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return ret;
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/* enable RXC clock when no wire plug */
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val = ytphy_read_ext(phydev, 0xc);
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if (val < 0)
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return val;
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val &= ~(1 << 12);
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ret = ytphy_write_ext(phydev, 0xc, val);
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if (ret < 0)
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return ret;
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/* output SyncE clock (125mhz) even link is down */
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ret = ytphy_write_ext(phydev, 0xa012, 0x38);
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if (ret < 0)
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return ret;
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/* disable rgmii clk 2ns delay */
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val = ytphy_read_ext(phydev, 0xa001);
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if (val < 0)
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return val;
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val &= ~(1 << 8);
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ret = ytphy_write_ext(phydev, 0xa001, val);
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if (ret < 0)
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return ret;
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/* setup delay */
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val = (1 << 10) | (0xf << 4) | 5;
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ret = ytphy_write_ext(phydev, 0xa003, val);
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if (ret < 0)
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return ret;
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/* LED0: Unused/Off, LED1: Link, LED2: Activity, 8Hz */
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ytphy_write_ext(phydev, 0xa00b, 0xe004);
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ytphy_write_ext(phydev, 0xa00c, 0);
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ytphy_write_ext(phydev, 0xa00d, 0x2600);
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ytphy_write_ext(phydev, 0xa00e, 0x0070);
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ytphy_write_ext(phydev, 0xa00f, 0x000a);
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return 0;
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}
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static int yt8521_config_intr(struct phy_device *phydev)
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{
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int val;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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val = BIT(14) | BIT(13) | BIT(11) | BIT(10);
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else
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val = 0;
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return phy_write(phydev, REG_INT_MASK, val);
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}
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static int yt8521_ack_interrupt(struct phy_device *phydev)
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{
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int val;
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val = phy_read(phydev, REG_INT_STATUS);
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phydev_dbg(phydev, "intr status 0x04%x\n", val);
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return (val < 0) ? val : 0;
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}
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static struct phy_driver ytphy_drvs[] = {
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{
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.phy_id = PHY_ID_YT8010,
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.name = "YT8010 Automotive Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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.features = PHY_BASIC_FEATURES,
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.config_aneg = yt8010_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_YT8510,
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.name = "YT8510 100/10Mb Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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.features = PHY_BASIC_FEATURES,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_YT8511,
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.name = "YT8511 Gigabit Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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.features = PHY_GBIT_FEATURES,
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.read_status = genphy_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = PHY_ID_YT8512,
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.name = "YT8512 Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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.features = PHY_BASIC_FEATURES,
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.config_init = yt8512_config_init,
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.read_status = yt8512_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = PHY_ID_YT8512B,
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.name = "YT8512B Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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.features = PHY_BASIC_FEATURES,
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.config_init = yt8512_config_init,
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.read_status = yt8512_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = PHY_ID_YT8521,
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.name = "YT8521 Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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/* PHY_GBIT_FEATURES */
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.config_init = yt8521_config_init,
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.ack_interrupt = yt8521_ack_interrupt,
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.config_intr = yt8521_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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/* same as 8521 */
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.phy_id = PHY_ID_YT8531S,
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.name = "YT8531S Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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/* PHY_GBIT_FEATURES */
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.config_init = yt8521_config_init,
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.ack_interrupt = yt8521_ack_interrupt,
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.config_intr = yt8521_config_intr,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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/* same as 8511 */
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.phy_id = PHY_ID_YT8531,
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.name = "YT8531 Gigabit Ethernet",
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.phy_id_mask = MOTORCOMM_PHY_ID_MASK,
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.features = PHY_GBIT_FEATURES,
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.config_init = yt8511_config_init,
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.read_status = genphy_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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},
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};
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module_phy_driver(ytphy_drvs);
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MODULE_DESCRIPTION("Motorcomm PHY driver");
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MODULE_AUTHOR("Leilei Zhao");
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MODULE_LICENSE("GPL");
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static struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
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{ PHY_ID_YT8010, MOTORCOMM_PHY_ID_MASK },
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{ PHY_ID_YT8510, MOTORCOMM_PHY_ID_MASK },
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{ PHY_ID_YT8511, MOTORCOMM_PHY_ID_MASK },
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{ PHY_ID_YT8512, MOTORCOMM_PHY_ID_MASK },
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{ PHY_ID_YT8512B, MOTORCOMM_PHY_ID_MASK },
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{ PHY_ID_YT8521, MOTORCOMM_PHY_ID_MASK },
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{ PHY_ID_YT8531S, MOTORCOMM_PHY_ID_8531_MASK },
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{ PHY_ID_YT8531, MOTORCOMM_PHY_ID_8531_MASK },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
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73
target/linux/rockchip/files/include/linux/motorcomm_phy.h
Normal file
73
target/linux/rockchip/files/include/linux/motorcomm_phy.h
Normal file
@ -0,0 +1,73 @@
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/*
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* include/linux/motorcomm_phy.h
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*
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* Motorcomm PHY IDs
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _MOTORCOMM_PHY_H
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#define _MOTORCOMM_PHY_H
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#define MOTORCOMM_PHY_ID_MASK 0x00000fff
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#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff
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#define PHY_ID_YT8010 0x00000309
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#define PHY_ID_YT8510 0x00000109
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#define PHY_ID_YT8511 0x0000010a
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#define PHY_ID_YT8512 0x00000118
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#define PHY_ID_YT8512B 0x00000128
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#define PHY_ID_YT8521 0x0000011a
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#define PHY_ID_YT8531S 0x4f51e91a
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#define PHY_ID_YT8531 0x4f51e91b
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#define REG_PHY_SPEC_STATUS 0x11
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#define REG_INT_MASK 0x12
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#define REG_INT_STATUS 0x13
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#define REG_DEBUG_ADDR_OFFSET 0x1e
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#define REG_DEBUG_DATA 0x1f
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#define YT8511_EXTREG_SLEEP_CONTROL1 0x27
|
||||
#define YT8511_EN_SLEEP_SW_BIT 15
|
||||
|
||||
#define YT8512_EXTREG_AFE_PLL 0x50
|
||||
#define YT8512_EXTREG_EXTEND_COMBO 0x4000
|
||||
#define YT8512_EXTREG_LED0 0x40c0
|
||||
#define YT8512_EXTREG_LED1 0x40c3
|
||||
|
||||
#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
|
||||
|
||||
#define YT_SOFTWARE_RESET 0x8000
|
||||
|
||||
#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
|
||||
#define YT8512_CONTROL1_RMII_EN 0x0001
|
||||
#define YT8512_LED0_ACT_BLK_IND 0x1000
|
||||
#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
|
||||
#define YT8512_LED0_BT_BLK_EN 0x0002
|
||||
#define YT8512_LED0_HT_BLK_EN 0x0004
|
||||
#define YT8512_LED0_COL_BLK_EN 0x0008
|
||||
#define YT8512_LED0_BT_ON_EN 0x0010
|
||||
#define YT8512_LED1_BT_ON_EN 0x0010
|
||||
#define YT8512_LED1_TXACT_BLK_EN 0x0100
|
||||
#define YT8512_LED1_RXACT_BLK_EN 0x0200
|
||||
#define YT8512_SPEED_MODE 0xc000
|
||||
#define YT8512_DUPLEX 0x2000
|
||||
|
||||
#define YT8512_SPEED_MODE_BIT 14
|
||||
#define YT8512_DUPLEX_BIT 13
|
||||
#define YT8512_EN_SLEEP_SW_BIT 15
|
||||
|
||||
#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
|
||||
#define YT8521_EN_SLEEP_SW_BIT 15
|
||||
|
||||
#define YT8521_SPEED_MODE 0xc000
|
||||
#define YT8521_DUPLEX 0x2000
|
||||
#define YT8521_SPEED_MODE_BIT 14
|
||||
#define YT8521_DUPLEX_BIT 13
|
||||
#define YT8521_LINK_STATUS_BIT 10
|
||||
|
||||
#endif /* _MOTORCOMM_PHY_H */
|
||||
@ -0,0 +1,39 @@
|
||||
From 5d6862cc5eac1679d7a4ef388f7c9bbc70e76770 Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Mon, 5 Jul 2021 17:03:00 +0800
|
||||
Subject: [PATCH] net: phy: Add driver for Motorcomm YT85xx PHYs
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/net/phy/Kconfig | 5 +
|
||||
drivers/net/phy/Makefile | 1 +
|
||||
drivers/net/phy/motorcomm.c | 346 ++++++++++++++++++++++++++++++++++
|
||||
include/linux/motorcomm_phy.h | 68 +++++++
|
||||
4 files changed, 420 insertions(+)
|
||||
create mode 100644 drivers/net/phy/motorcomm.c
|
||||
create mode 100644 include/linux/motorcomm_phy.h
|
||||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -519,6 +519,11 @@ config MICROSEMI_PHY
|
||||
---help---
|
||||
Currently supports VSC8514, VSC8530, VSC8531, VSC8540 and VSC8541 PHYs
|
||||
|
||||
+config MOTORCOMM_PHY
|
||||
+ tristate "Motorcomm PHYs"
|
||||
+ ---help---
|
||||
+ Supports the YT8010, YT8510, YT8511, YT8512 PHYs.
|
||||
+
|
||||
config NATIONAL_PHY
|
||||
tristate "National Semiconductor PHYs"
|
||||
---help---
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -98,6 +98,7 @@ obj-$(CONFIG_MICREL_PHY) += micrel.o
|
||||
obj-$(CONFIG_MICROCHIP_PHY) += microchip.o
|
||||
obj-$(CONFIG_MICROCHIP_T1_PHY) += microchip_t1.o
|
||||
obj-$(CONFIG_MICROSEMI_PHY) += mscc.o
|
||||
+obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm.o
|
||||
obj-$(CONFIG_NATIONAL_PHY) += national.o
|
||||
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
|
||||
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
|
||||
Loading…
Reference in New Issue
Block a user