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target/rockchip: rk806 backport supports for customize reset-mode

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Equivalent to `pmic-reset-func` in the Rockchip SDK

Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
This commit is contained in:
Liangbin Lian 2025-12-17 13:51:50 +08:00
parent dbdd5ffd3a
commit ba025fd786
4 changed files with 228 additions and 0 deletions
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28
target/linux/rockchip/patches-6.6/031-03-v6.7-dt-bindings-mfd-rk806-Allow-system-power-controller-.patch Normal file
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From 6243b687417686873322c8391fad39c25f1cfb6a Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Thu, 19 Oct 2023 18:57:24 +0200
Subject: [PATCH] dt-bindings: mfd: rk806: Allow system-power-controller
property
Declare support for this property.
Signed-off-by: Ondrej Jirman <megi@xff.cz>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20231019165732.3818789-3-megi@xff.cz
Signed-off-by: Lee Jones <lee@kernel.org>
---
Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml | 2 ++
1 file changed, 2 insertions(+)
--- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
+++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
@@ -29,6 +29,8 @@ properties:
'#gpio-cells':
const: 2
+ system-power-controller: true
+
vcc1-supply:
description:
The input supply for dcdc-reg1.

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target/linux/rockchip/patches-6.6/317-1-v6.17-dt-bindings-mfd-rk806-Allow-to-customize-PMIC-reset-.patch Normal file
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From f5971da5eddf2c4d0ffda3ea343274a66d5ca3a8 Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@cherry.de>
Date: Fri, 27 Jun 2025 12:53:53 +0200
Subject: [PATCH 1/3] dt-bindings: mfd: rk806: Allow to customize PMIC reset
mode
The RK806 PMIC allows to configure its reset/restart behavior whenever
the PMIC is reset either programmatically or via some external pins
(e.g. PWRCTRL or RESETB).
The following modes exist:
- 0; restart PMU,
- 1; reset all power off reset registers and force state to switch to
ACTIVE mode,
- 2; same as mode 1 and also pull RESETB pin down for 5ms,
For example, some hardware may require a full restart (mode 0) in order
to function properly as regulators are shortly interrupted in this mode.
This is the case for RK3588 Jaguar and RK3588 Tiger which have a
companion microcontroller running on an independent power supply and
monitoring the PMIC power rail to know the state of the main system.
When it detects a restart, it resets its own IPs exposed to the main
system as if to simulate its own reset. Failing to perform this fake
reset of the microcontroller may break things (e.g. watchdog not
automatically disabled, buzzer still running until manually disabled,
leftover configuration from previous main system state, etc...).
Some other systems may be depending on the power rails to not be
interrupted even for a small amount of time[1].
This allows to specify how the PMIC should perform on the hardware level
and may differ between hardware designs, so a DT property seems
warranted. I unfortunately do not see how this could be made generic
enough to make it a non-vendor property.
[1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-1-ce05d041b45f@cherry.de
Signed-off-by: Lee Jones <lee@kernel.org>
---
.../bindings/mfd/rockchip,rk806.yaml | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
--- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
+++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
@@ -31,6 +31,27 @@ properties:
system-power-controller: true
+ rockchip,reset-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ description:
+ Mode to use when a reset of the PMIC is triggered.
+
+ The reset can be triggered either programmatically, via one of
+ the PWRCTRL pins (provided additional configuration) or
+ asserting RESETB pin low.
+
+ The following modes are supported
+
+ - 0; restart PMU,
+ - 1; reset all power off reset registers and force state to
+ switch to ACTIVE mode,
+ - 2; same as mode 1 and also pull RESETB pin down for 5ms,
+
+ For example, some hardware may require a full restart (mode 0)
+ in order to function properly as regulators are shortly
+ interrupted in this mode.
+
vcc1-supply:
description:
The input supply for dcdc-reg1.

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target/linux/rockchip/patches-6.6/317-2-v6.17-mfd-rk8xx-core-Allow-to-customize-RK806-reset-mode.patch Normal file
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From 83077073d6d217f15fdd5823ddebb6b01b63e79e Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@cherry.de>
Date: Fri, 27 Jun 2025 12:53:54 +0200
Subject: [PATCH 2/3] mfd: rk8xx-core: Allow to customize RK806 reset mode
The RK806 PMIC has a bitfield for configuring the restart/reset behavior
(which I assume Rockchip calls "function") whenever the PMIC is reset
either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL
or RESETB pins.
For RK806, the following values are possible for RST_FUN:
0b00 means "Restart PMU"
0b01 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode"
0b10 means "Reset all the power off reset registers, forcing
the state to switch to ACTIVE mode, and simultaneously
pull down the RESETB PIN for 5mS before releasing"
0b11 means the same as for 0b10 just above.
This adds the appropriate logic in the driver to parse the new
rockchip,reset-mode DT property to pass this information. It just
happens that the values in the binding match the values to write in the
bitfield so no mapping is necessary.
If it is missing, the register is left untouched and relies either on
the silicon default or on whatever was set earlier in the boot stages
(e.g. the bootloader).
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-2-ce05d041b45f@cherry.de
Signed-off-by: Lee Jones <lee@kernel.org>
---
drivers/mfd/rk8xx-core.c | 12 ++++++++++++
include/linux/mfd/rk808.h | 2 ++
2 files changed, 14 insertions(+)
--- a/drivers/mfd/rk8xx-core.c
+++ b/drivers/mfd/rk8xx-core.c
@@ -10,6 +10,7 @@
* Author: Wadim Egorov <w.egorov@phytec.de>
*/
+#include <linux/bitfield.h>
#include <linux/interrupt.h>
#include <linux/mfd/rk808.h>
#include <linux/mfd/core.h>
@@ -604,6 +605,7 @@ int rk8xx_probe(struct device *dev, int
int lp_off_time, pwron_key = 0;
u32 val;
int nr_pre_init_regs;
+ u32 rst_fun = 0;
int nr_cells;
int ret;
int i;
@@ -632,6 +634,16 @@ int rk8xx_probe(struct device *dev, int
cells = rk806s;
nr_cells = ARRAY_SIZE(rk806s);
dual_support = IRQF_SHARED;
+
+ ret = device_property_read_u32(dev, "rockchip,reset-mode", &rst_fun);
+ if (ret)
+ break;
+
+ ret = regmap_update_bits(rk808->regmap, RK806_SYS_CFG3, RK806_RST_FUN_MSK,
+ FIELD_PREP(RK806_RST_FUN_MSK, rst_fun));
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to configure requested restart/reset behavior\n");
break;
case RK808_ID:
pwron_key = RK808_DEVCTRL_REG;
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -675,6 +675,8 @@ enum rk806_pin_dr_sel {
#define RK806_INT_POL_H BIT(1)
#define RK806_INT_POL_L 0
+/* SYS_CFG3 */
+#define RK806_RST_FUN_MSK GENMASK(7, 6)
#define RK806_SLAVE_RESTART_FUN_MSK BIT(1)
#define RK806_SLAVE_RESTART_FUN_EN BIT(1)
#define RK806_SLAVE_RESTART_FUN_OFF 0

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target/linux/rockchip/patches-6.6/317-3-v6.17-arm64-dts-rockchip-add-header-for-RK8XX-PMIC-constan.patch Normal file
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From d50f7afbe1f6461cc4e10b53c2f532363dc3031c Mon Sep 17 00:00:00 2001
From: Quentin Schulz <quentin.schulz@cherry.de>
Date: Fri, 27 Jun 2025 12:53:55 +0200
Subject: [PATCH 3/3] arm64: dts: rockchip: add header for RK8XX PMIC constants
To make it easier to read the device tree, let's add constants for the
rockchip,reset-mode property values that are currently only applicable
to RK806 PMIC.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
[dt-maintainers did not consider this part of the binding, so we're
keeping the header in the devicetree directory]
Link: https://lore.kernel.org/r/20250627-rk8xx-rst-fun-v4-3-ce05d041b45f@cherry.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm64/boot/dts/rockchip/rk8xx.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk8xx.h
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk8xx.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */
+/*
+ * Device Tree defines for Rockchip RK8xx PMICs
+ *
+ * Copyright 2025 Cherry Embedded Solutions GmbH
+ *
+ * Author: Quentin Schulz <quentin.schulz@cherry.de>
+ */
+
+#ifndef _DT_MFD_ROCKCHIP_RK8XX_H
+#define _DT_MFD_ROCKCHIP_RK8XX_H
+
+/* For use with rockchip,reset-mode property */
+#define RK806_RESTART 0
+#define RK806_RESET 1
+#define RK806_RESET_NOTIFY 2
+
+#endif