From e167fbb1b82c3c5cec7363f689b408a070acb567 Mon Sep 17 00:00:00 2001
From: Liangbin Lian <jjm2473@gmail.com>
Date: Sat, 20 May 2023 10:27:03 +0800
Subject: [PATCH] target/rockchip: fix hsa-bh2 dts

---
 .../rockchip/rk3568/dts/rk3568-hsa-bh2.dts    | 54 ++++++++++++++++++-
 1 file changed, 53 insertions(+), 1 deletion(-)

diff --git a/target/linux/rockchip/rk3568/dts/rk3568-hsa-bh2.dts b/target/linux/rockchip/rk3568/dts/rk3568-hsa-bh2.dts
index 5b08186a2a..dbb3da4b6e 100644
--- a/target/linux/rockchip/rk3568/dts/rk3568-hsa-bh2.dts
+++ b/target/linux/rockchip/rk3568/dts/rk3568-hsa-bh2.dts
@@ -13,7 +13,6 @@
 #include <dt-bindings/display/drm_mipi_dsi.h>
 #include <dt-bindings/sensor-dev.h>
 #include "rk3568.dtsi"
-#include "rk3568-linux.dtsi"
 
 / {
     compatible = "hsa,bh2", "rockchip,rk3568";
@@ -25,6 +24,39 @@
 		led-upgrade = &led_sys;
 	};
 
+	chosen: chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTLABEL=rootfs rootfstype=ext4 ro rootwait overlayroot=device:dev=PARTLABEL=userdata,fstype=ext4,mkfs=1 coherent_pool=1m systemd.gpt_auto=0 cgroup_enable=memory swapaccount=1";
+	};
+
+	fiq-debugger {
+		compatible = "rockchip,fiq-debugger";
+		rockchip,serial-id = <2>;
+		rockchip,wake-irq = <0>;
+		/* If enable uart uses irq instead of fiq */
+		rockchip,irq-mode-enable = <1>;
+		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
+		interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m0_xfer>;
+		status = "okay";
+	};
+
+	debug: debug@fd904000 {
+		compatible = "rockchip,debug";
+		reg = <0x0 0xfd904000 0x0 0x1000>,
+			<0x0 0xfd905000 0x0 0x1000>,
+			<0x0 0xfd906000 0x0 0x1000>,
+			<0x0 0xfd907000 0x0 0x1000>;
+	};
+
+	cspmu: cspmu@fd90c000 {
+		compatible = "rockchip,cspmu";
+		reg = <0x0 0xfd90c000 0x0 0x1000>,
+			<0x0 0xfd90d000 0x0 0x1000>,
+			<0x0 0xfd90e000 0x0 0x1000>,
+			<0x0 0xfd90f000 0x0 0x1000>;
+	};
+
     dc_12v: dc-12v {
         compatible = "regulator-fixed";
         regulator-name = "dc_12v";
@@ -112,6 +144,25 @@
 	};
 };
 
+&reserved_memory {
+	ramoops: ramoops@110000 {
+		compatible = "ramoops";
+		reg = <0x0 0x110000 0x0 0xf0000>;
+		record-size = <0x20000>;
+		console-size = <0x80000>;
+		ftrace-size = <0x00000>;
+		pmsg-size = <0x50000>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+&rockchip_suspend {
+	status = "okay";
+};
+
 &pmu_io_domains {
     status = "okay";
     pmuio1-supply = <&vcc3v3_pmu>;
@@ -691,6 +742,7 @@
 
 &vop {
     status = "okay";
+    disable-win-move;
     assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
     assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
 };