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package/r8125: update patches

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This commit is contained in:
Liangbin Lian 2025-04-07 21:13:43 +08:00
parent f3793dafe9
commit ee339a1fde
4 changed files with 158 additions and 2 deletions
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2
package/kernel/r8125/Makefile
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@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=r8125
PKG_VERSION:=9.014.01
PKG_RELEASE:=2
PKG_RELEASE:=3
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://github.com/openwrt/rtl8125/releases/download/$(PKG_VERSION)

109
package/kernel/r8125/patches/100-add-LED-configuration-from-OF.patch Normal file
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@ -0,0 +1,109 @@
From 038d93935f67bc8a196355d2b6199d1286c53557 Mon Sep 17 00:00:00 2001
From: jjm2473 <jjm2473@gmail.com>
Date: Wed, 26 Jun 2024 10:59:50 +0800
Subject: [PATCH] 100-add-LED-configuration-from-OF
see https://mail.coreboot.org/hyperkitty/list/coreboot-gerrit@coreboot.org/thread/4SIVEXWBE5MNR4ONIW2D5MMEKHR47CJC/
---
src/r8125.h | 5 +++++
src/r8125_n.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
--- a/src/r8125.h
+++ b/src/r8125.h
@@ -1382,6 +1382,7 @@ enum RTL8125_registers {
CounterAddrLow = 0x10,
CounterAddrHigh = 0x14,
CustomLED = 0x18,
+ LEDSEL0 = 0x18,
TxDescStartAddrLow = 0x20,
TxDescStartAddrHigh = 0x24,
TxHDescStartAddrLow = 0x28,
@@ -1418,7 +1419,11 @@ enum RTL8125_registers {
INT_CFG1_8125 = 0x7A,
EPHY_RXER_NUM = 0x7C,
EPHYAR = 0x80,
+ LEDSEL2 = 0x84,
+ LEDSEL1 = 0x86,
TimeInt2 = 0x8C,
+ LEDFEATURE = 0x94,
+ LEDSEL3 = 0x96,
OCPDR = 0xB0,
MACOCP = 0xB0,
OCPAR = 0xB4,
--- a/src/r8125_n.c
+++ b/src/r8125_n.c
@@ -43,6 +43,7 @@
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/mii.h>
+#include <linux/of.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/interrupt.h>
@@ -14715,6 +14716,56 @@ rtl8125_setup_mqs_reg(struct rtl8125_pri
tp->imr_reg[i] = (u16)(IMR1_8125 + (i - 1) * 4);
}
+/*
+ * Refer to RTL8125 datasheet 5.Customizable LED Configuration
+ * Register Name IO Address
+ * LEDSEL0 0x18
+ * LEDSEL1 0x86
+ * LEDSEL2 0x84
+ * LEDSEL3 0x96
+ * LEDFEATURE 0x94
+ *
+ * LEDSEL Bit[] Description
+ * Bit0 Link10M
+ * Bit1 Link100M
+ * Bit3 Link1000M
+ * Bit5 Link2.5G
+ * Bit9 ACT
+ * Bit10 preboot enable
+ * Bit11 lp enable
+ * Bit12 active low/high
+ *
+ * LEDFEATURE Description
+ * Bit0 LED Table V1/V2
+ * Bit1~3 Reserved
+ * Bit4~5 LED Blinking Duty Cycle 12.5%/ 25%/ 50%/ 75%
+ * Bit6~7 LED Blinking Freq. 240ms/160ms/80ms/Link-Speed-Dependent
+ */
+static int
+rtl8125_led_configuration(struct rtl8125_private *tp)
+{
+ const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 }; /* LEDSEL 0-3 */
+ u32 led_data[4];
+ u8 led_feature;
+ int ret, i;
+
+ ret = of_property_read_u32_array(tp->pci_dev->dev.of_node,
+ "realtek,led-data", led_data, 4);
+
+ if (!ret) {
+ for (i = 0; i < 4; i++)
+ RTL_W16(tp, led_regs[i], led_data[i]);
+ }
+
+ ret = of_property_read_u8(tp->pci_dev->dev.of_node,
+ "realtek,led-feature", &led_feature);
+
+ if (!ret) {
+ RTL_W8(tp, LEDFEATURE, led_feature);
+ }
+ return 0;
+}
+
static void
rtl8125_init_software_variable(struct net_device *dev)
{
@@ -15318,6 +15369,8 @@ rtl8125_init_software_variable(struct ne
else if (tp->InitRxDescType == RX_DESC_RING_TYPE_4)
tp->rtl8125_rx_config &= ~EnableRxDescV4_1;
+ rtl8125_led_configuration(tp);
+
tp->NicCustLedValue = RTL_R16(tp, CustomLED);
tp->wol_opts = rtl8125_get_hw_wol(tp);

2
package/kernel/r8125/patches/102-rework-2_5G-on-8162.patch
View File

@ -9,7 +9,7 @@ Subject: [PATCH] rework 2.5G on [10ec:8162]
--- a/src/r8125_n.c
+++ b/src/r8125_n.c
@@ -7903,7 +7903,7 @@ static void rtl8125_get_mac_version(struct rtl8125_private *tp)
@@ -7904,7 +7904,7 @@ static void rtl8125_get_mac_version(stru
break;
}

47
package/kernel/r8125/patches/110-detail-kernel-warning.patch Normal file
View File

@ -0,0 +1,47 @@
--- a/src/r8125_n.c
+++ b/src/r8125_n.c
@@ -3224,7 +3224,7 @@ static void mdio_real_direct_write_phy_o
int i;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
- WARN_ON_ONCE(RegAddr % 2);
+ WARN_ONCE(RegAddr % 2, "RegAddr not aligned");
#endif
data32 = RegAddr/2;
data32 <<= OCPR_Addr_Reg_shift;
@@ -3317,7 +3317,7 @@ static u32 mdio_real_direct_read_phy_ocp
int i, value = 0;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
- WARN_ON_ONCE(RegAddr % 2);
+ WARN_ONCE(RegAddr % 2, "RegAddr not aligned");
#endif
data32 = RegAddr/2;
data32 <<= OCPR_Addr_Reg_shift;
@@ -3451,7 +3451,7 @@ void rtl8125_mac_ocp_write(struct rtl812
u32 data32;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
- WARN_ON_ONCE(reg_addr % 2);
+ WARN_ONCE(reg_addr % 2, "reg_addr not aligned");
#endif
data32 = reg_addr/2;
@@ -3468,7 +3468,7 @@ u16 rtl8125_mac_ocp_read(struct rtl8125_
u16 data16 = 0;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
- WARN_ON_ONCE(reg_addr % 2);
+ WARN_ONCE(reg_addr % 2, "reg_addr not aligned");
#endif
data32 = reg_addr/2;
@@ -8020,7 +8020,7 @@ rtl8125_wait_phy_ups_resume(struct net_d
}
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
- WARN_ON_ONCE(i == 100);
+ WARN_ONCE(i == 100, "wait phy up timeout");
#endif
break;
default: