155 lines
3.3 KiB
Plaintext
155 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2022 Flippy <flippy@sina.com>
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*/
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/dts-v1/;
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#include "rk3568-roc-k40pro.dtsi"
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#include "rk3568-ip.dtsi"
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#include "rk3568-ip-rk809.dtsi"
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/ {
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compatible = "roceos,k40prov3", "rockchip,rk3568";
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model = "ROCEOS K40PRO V3";
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eth_order = "fe010000.ethernet,fe2a0000.ethernet,0001:*1:00.0,0000:01:00.0";
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kdebug = "0";
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hwmodel_id = "K40PROV3";
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r8168_led = <0x708>;
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hw_support = "hdmi";
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aliases {
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ethernet2 = &pcie_eth2;
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ethernet3 = &pcie_eth3;
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mmc2 = &sdmmc2;
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};
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pwr-net-25g {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_25g_en>;
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regulator-name = "vcc-pwr-25g";
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regulator-always-on;
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vin-supply = <&vcc3v3_sys>;
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};
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vcc3v3_nvme: vcc3v3-nvme-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_nvme";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
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vin-supply = <&dc_12v>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc3v3_nvme_en>;
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};
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};
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//配置WL_REG_ON引脚
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&sdio_pwrseq {
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status = "okay";
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reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
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post-power-on-delay-ms = <200>;
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};
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// 配置WL_HOST_WAKE引脚，OOB模式时，该引脚必须配置
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&wireless_wlan {
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_host_wake_irq>;
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WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
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wifi_chip_type = "ap6255";
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status = "okay";
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};
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&wireless_bluetooth {
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compatible = "bluetooth-platdata";
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clocks = <&rk809 1>;
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clock-names = "ext_clock";
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//wifi-bt-power-toggle;
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uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "rts_gpio";
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pinctrl-0 = <&uart8m0_rtsn>;
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pinctrl-1 = <&uart8_gpios>;
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BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
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BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
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BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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// wifi
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&sdmmc2 {
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max-frequency = <150000000>;
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supports-sdio;
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-sdio-irq;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
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sd-uhs-sdr104;
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status = "okay";
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};
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&pcie2x1 {
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rockchip,init-delay-ms = <100>;
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reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pcie@00 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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pcie_eth3: pcie-eth@00,0 {
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compatible = "pci10ec,8125";
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reg = <0x000000 0 0 0 0>;
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realtek,led-data = <0 0 0x200 0x02B>;
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realtek,led-feature = /bits/ 8 <0xC0>;
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};
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};
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};
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&pcie3x1 {
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reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pcie@10 {
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reg = <0x00100000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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pcie_eth2: pcie-eth@10,0 {
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compatible = "pci10ec,8125";
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reg = <0x000000 0 0 0 0>;
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realtek,led-data = <0 0 0x200 0x02B>;
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realtek,led-feature = /bits/ 8 <0xC0>;
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};
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};
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};
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&pcie3x2 {
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reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_nvme>;
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status = "okay";
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};
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&pinctrl {
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pwr-25g {
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pwr_25g_en: pwr-25g-en {
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rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
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};
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};
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nvme {
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vcc3v3_nvme_en: vcc3v3-nvme-en {
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rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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