48ec8469fd
This add a pending version of the Airoha PCS driver to add support for
External PHY. The Airoha PCS driver will receive some minor modification
once we the PCS subsystem will be defined upstream.
Add all the required node for GDM2 and GDM4 and enable the PCS config.
(cherry picked from commit c3d70b1ae5)
[ fix conflict error ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
53 lines
1.9 KiB
Diff
53 lines
1.9 KiB
Diff
From 6fbb7d72520393a3d447399799d436f17c03ff24 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Fri, 17 Jan 2025 10:29:52 +0100
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Subject: [PATCH 5/9] net: airoha: drop redundant GDM3/4 define
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The GDM FWD register are all the same hence it's redundant to have
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specific define for GDM3 and GDM4. Drop the redundant define and use the
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generic macro.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/net/ethernet/airoha/airoha_eth.c | 4 ++--
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drivers/net/ethernet/airoha/airoha_regs.h | 8 +-------
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2 files changed, 3 insertions(+), 9 deletions(-)
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--- a/drivers/net/ethernet/airoha/airoha_eth.c
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+++ b/drivers/net/ethernet/airoha/airoha_eth.c
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@@ -507,8 +507,8 @@ static int airoha_fe_init(struct airoha_
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FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) |
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FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22));
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- airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK);
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- airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK);
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+ airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN);
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+ airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN);
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airoha_fe_crsn_qsel_init(eth);
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--- a/drivers/net/ethernet/airoha/airoha_regs.h
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+++ b/drivers/net/ethernet/airoha/airoha_regs.h
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@@ -128,6 +128,7 @@
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GENMASK(4 + (((_n) % 4) << 3), (((_n) % 4) << 3))
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#define REG_GDM_FWD_CFG(_n) GDM_BASE(_n)
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+#define GDM_PAD_EN BIT(28)
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#define GDM_DROP_CRC_ERR BIT(23)
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#define GDM_IP4_CKSUM BIT(22)
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#define GDM_TCP_CKSUM BIT(21)
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@@ -349,13 +350,6 @@
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#define MBI_RX_AGE_SEL_MASK GENMASK(26, 25)
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#define MBI_TX_AGE_SEL_MASK GENMASK(18, 17)
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-#define REG_GDM3_FWD_CFG GDM3_BASE
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-#define GDM3_PAD_EN_MASK BIT(28)
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-
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-#define REG_GDM4_FWD_CFG GDM4_BASE
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-#define GDM4_PAD_EN_MASK BIT(28)
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-#define GDM4_SPORT_OFFSET0_MASK GENMASK(11, 8)
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-
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#define REG_GDM4_SRC_PORT_SET (GDM4_BASE + 0x23c)
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#define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
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#define GDM4_SPORT_OFF1_MASK GENMASK(15, 12)
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