ade13ffdaa
Based on: *2dc8224e37/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c* https://lore.kernel.org/all/20241016-b4-rk3588-bridge-upstream-v10-1-87ef92a6d14e@collabora.com/ *a52dffaa46/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c*a52dffaa46/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c*a52dffaa46/drivers/gpu/drm/rockchip/rockchip_vop2_reg.cSigned-off-by: Liangbin Lian <jjm2473@gmail.com>
242 lines
9.7 KiB
Diff
242 lines
9.7 KiB
Diff
From 85bc910629a9f31b879aeb4f1a1c5fa211406f4a Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Tue, 18 Mar 2025 14:35:42 +0200
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Subject: [PATCH 07/11] phy: rockchip: samsung-hdptx: Avoid Hz<->hHz unit
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conversion overhead
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The ropll_tmds_cfg table used to identify the configuration params for
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the supported rates expects the search key, i.e. bit_rate member of
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struct ropll_config, to be provided in hHz rather than Hz (1 hHz = 100
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Hz). This requires multiple conversions between these units being
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performed at runtime.
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Improve implementation clarity and efficiency by consistently using the
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Hz unit throughout driver's internal data structures and functions.
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Also rename the rather misleading struct member.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-8-8cb1678e7663@collabora.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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.../phy/rockchip/phy-rockchip-samsung-hdptx.c | 79 +++++++++----------
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1 file changed, 39 insertions(+), 40 deletions(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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index de333b743810..36b01a2e414b 100644
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--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -196,7 +196,7 @@
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#define HDMI20_MAX_RATE 600000000
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struct ropll_config {
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- u32 bit_rate;
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+ unsigned long long rate;
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u8 pms_mdiv;
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u8 pms_mdiv_afc;
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u8 pms_pdiv;
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@@ -259,45 +259,45 @@ struct rk_hdptx_phy {
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};
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static const struct ropll_config ropll_tmds_cfg[] = {
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- { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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+ { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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+ { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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+ { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
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+ { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
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1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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+ { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
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+ { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
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+ { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
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0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
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+ { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
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1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
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+ { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
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1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
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+ { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
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1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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+ { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
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+ { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
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+ { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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+ { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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+ { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
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+ { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
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+ { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
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1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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+ { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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+ { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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- { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
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+ { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
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1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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};
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@@ -659,10 +659,10 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
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regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
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}
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-static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
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+static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
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struct ropll_config *cfg)
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{
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- const unsigned int fout = data_rate / 2, fref = 24000;
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+ const unsigned int fout = div_u64(rate, 200), fref = 24000;
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unsigned long k = 0, lc, k_sub, lc_sub;
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unsigned int fvco, sdc;
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u32 mdiv, sdiv, n = 8;
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@@ -732,14 +732,14 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
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}
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static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
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- unsigned int rate)
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+ unsigned long long rate)
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{
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const struct ropll_config *cfg = NULL;
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struct ropll_config rc = {0};
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int ret, i;
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for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
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- if (rate == ropll_tmds_cfg[i].bit_rate) {
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+ if (rate == ropll_tmds_cfg[i].rate) {
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cfg = &ropll_tmds_cfg[i];
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break;
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}
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@@ -753,8 +753,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
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}
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}
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- dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n",
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- cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
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+ dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n",
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+ __func__, rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
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cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
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rk_hdptx_pre_power_up(hdptx);
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@@ -793,19 +793,19 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
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ret = rk_hdptx_post_enable_pll(hdptx);
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if (!ret)
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- hdptx->rate = rate * 100;
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+ hdptx->rate = rate;
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return ret;
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}
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static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
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- unsigned int rate)
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+ unsigned long long rate)
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{
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rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
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regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
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- if (rate > HDMI14_MAX_RATE / 100) {
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+ if (rate > HDMI14_MAX_RATE) {
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/* For 1/40 bitrate clk */
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rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
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} else {
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@@ -823,7 +823,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
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}
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static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
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- unsigned int rate)
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+ unsigned long long rate)
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{
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u32 status;
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int ret;
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@@ -881,7 +881,7 @@ static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
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static int rk_hdptx_phy_power_on(struct phy *phy)
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{
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struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
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- int bus_width = phy_get_bus_width(hdptx->phy);
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+ unsigned long long rate;
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int ret;
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/*
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@@ -889,10 +889,10 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
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* from the HDMI bridge driver until phy_configure_opts_hdmi
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* becomes available in the PHY API.
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*/
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- unsigned int rate = bus_width & 0xfffffff;
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+ rate = phy_get_bus_width(hdptx->phy) & 0xfffffff;
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+ rate *= 100;
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- dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
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- __func__, bus_width, rate);
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+ dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, rate);
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ret = rk_hdptx_phy_consumer_get(hdptx, rate);
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if (ret)
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@@ -927,7 +927,7 @@ static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
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{
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struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
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- return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
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+ return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate);
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}
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static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
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@@ -948,18 +948,17 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
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static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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- u32 bit_rate = rate / 100;
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int i;
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if (rate > HDMI20_MAX_RATE)
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return rate;
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for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
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- if (bit_rate == ropll_tmds_cfg[i].bit_rate)
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+ if (rate == ropll_tmds_cfg[i].rate)
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break;
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if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
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- !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
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+ !rk_hdptx_phy_clk_pll_calc(rate, NULL))
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return -EINVAL;
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return rate;
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@@ -970,7 +969,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
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- return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
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+ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
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}
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static const struct clk_ops hdptx_phy_clk_ops = {
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--
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2.51.0
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