ade13ffdaa
Based on: *2dc8224e37/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c* https://lore.kernel.org/all/20241016-b4-rk3588-bridge-upstream-v10-1-87ef92a6d14e@collabora.com/ *a52dffaa46/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c*a52dffaa46/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c*a52dffaa46/drivers/gpu/drm/rockchip/rockchip_vop2_reg.cSigned-off-by: Liangbin Lian <jjm2473@gmail.com>
42 lines
1.8 KiB
Diff
42 lines
1.8 KiB
Diff
From 36afb795a27c8631a2e34ba1b761f0435eaaed25 Mon Sep 17 00:00:00 2001
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From: Algea Cao <algea.cao@rock-chips.com>
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Date: Sun, 27 Apr 2025 17:51:24 +0800
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Subject: [PATCH 09/11] phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output
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50.25MHz error
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When using HDMI PLL frequency division coefficient at 50.25MHz
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that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to
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get PHY LANE lock. Although the calculated values are within the
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allowable range of PHY PLL configuration.
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In order to fix the PHY LANE lock error and provide the expected
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50.25MHz output, manually compute the required PHY PLL frequency
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division coefficient and add it to ropll_tmds_cfg configuration
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table.
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Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
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Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Acked-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20250427095124.3354439-1-algea.cao@rock-chips.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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index 4c713616963a..be504439c767 100644
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--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -291,6 +291,8 @@ static const struct ropll_config ropll_tmds_cfg[] = {
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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{ 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
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1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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+ { 50250000ULL, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5,
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+ 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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{ 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
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1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
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{ 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
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--
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2.51.0
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