ade13ffdaa
Based on: *2dc8224e37/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c* https://lore.kernel.org/all/20241016-b4-rk3588-bridge-upstream-v10-1-87ef92a6d14e@collabora.com/ *a52dffaa46/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c*a52dffaa46/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c*a52dffaa46/drivers/gpu/drm/rockchip/rockchip_vop2_reg.cSigned-off-by: Liangbin Lian <jjm2473@gmail.com>
50 lines
2.0 KiB
Diff
50 lines
2.0 KiB
Diff
From 6bde631bd5caf3a5b6719c535d62b96fbd068a5e Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Tue, 28 Oct 2025 10:00:55 +0200
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Subject: [PATCH 10/11] phy: rockchip: samsung-hdptx: Reduce ROPLL loop
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bandwidth
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Due to its relatively low frequency, a noise stemming from the 24MHz PLL
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reference clock may traverse the low-pass loop filter of ROPLL, which
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could potentially generate some HDMI flash artifacts.
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Reduce ROPLL loop bandwidth in an attempt to mitigate the problem.
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Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
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Co-developed-by: Algea Cao <algea.cao@rock-chips.com>
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Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-2-ecc642a59d94@collabora.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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index be504439c767..bdc52495774d 100644
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--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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@@ -347,9 +347,7 @@ static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
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REG_SEQ0(CMN_REG(0043), 0x00),
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REG_SEQ0(CMN_REG(0044), 0x46),
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REG_SEQ0(CMN_REG(0045), 0x24),
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- REG_SEQ0(CMN_REG(0046), 0xff),
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REG_SEQ0(CMN_REG(0047), 0x00),
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- REG_SEQ0(CMN_REG(0048), 0x44),
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REG_SEQ0(CMN_REG(0049), 0xfa),
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REG_SEQ0(CMN_REG(004a), 0x08),
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REG_SEQ0(CMN_REG(004b), 0x00),
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@@ -422,6 +420,8 @@ static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
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REG_SEQ0(CMN_REG(0034), 0x00),
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REG_SEQ0(CMN_REG(003d), 0x40),
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REG_SEQ0(CMN_REG(0042), 0x78),
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+ REG_SEQ0(CMN_REG(0046), 0xdd),
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+ REG_SEQ0(CMN_REG(0048), 0x11),
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REG_SEQ0(CMN_REG(004e), 0x34),
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REG_SEQ0(CMN_REG(005c), 0x25),
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REG_SEQ0(CMN_REG(005e), 0x4f),
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--
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2.51.0
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