These instructions are for 64-bit load/store. On ARMv5TE, the CPU
requires addresses to be aligned to 64-bit. When misaligned, behavior is
undefined (effectively either loads the same word twice on LDRD, or
corrupts surrounding memory on STRD).
On ARMv6 and newer, unaligned access is safe.
Removing these instructions for ARMv5TE is necessary, because GCC
ignores alignment information in pointers and does unsafe optimizations
that have shown up as bugs in various places.
This patch was originally added more than 11 years ago in commit b050f87d13,
but got lost 6 years ago, when gcc 9.1 was added in 88c07c6552.
This primarily affects the kirkwood and ixp4xx targets
Signed-off-by: Felix Fietkau <nbd@nbd.name>
(cherry picked from commit c1c11120069b8e04ad4b0c6e815d2e3421944933)
6489f3ef89