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package/uboot-rk35xx: update gmac config

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This commit is contained in:
Liangbin Lian 2023-05-09 18:39:13 +08:00
parent 20edd5f89e
commit 47371102fa
2 changed files with 33 additions and 34 deletions
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32
package/boot/uboot-rk35/src/arch/arm/dts/rk3568-easepi-u-boot.dtsi
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@ -7,54 +7,54 @@
#include "rk3568-u-boot.dtsi"
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
phy-mode = "rgmii";
clock_in_out = "output";
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&gmac0_clkinout>;
&gmac0_rgmii_bus>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
tx_delay = <0x35>;
rx_delay = <0x2b>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
phy-mode = "rgmii";
clock_in_out = "output";
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&gmac1m1_clkinout>;
&gmac1m1_rgmii_bus>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
tx_delay = <0x42>;
rx_delay = <0x27>;
phy-handle = <&rgmii_phy1>;
status = "okay";

35
package/boot/uboot-rk35/src/arch/arm/dts/rk3568-easepi.dtsi
View File

@ -30,55 +30,54 @@
};
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
phy-mode = "rgmii";
clock_in_out = "output";
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
// assigned-clock-rates = <0>, <125000000>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&gmac0_clkinout>;
&gmac0_rgmii_bus>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
tx_delay = <0x35>;
rx_delay = <0x2b>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&gmac1 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
phy-mode = "rgmii";
clock_in_out = "output";
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
// assigned-clock-rates = <0>, <125000000>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&gmac1m1_clkinout>;
&gmac1m1_rgmii_bus>;
tx_delay = <0x4f>;
rx_delay = <0x26>;
tx_delay = <0x42>;
rx_delay = <0x27>;
phy-handle = <&rgmii_phy1>;
status = "okay";