target/rockchip: dts: fix rtl8211f phy addr on some boards

usually does not affect functionality, just aligns with the schematic
This commit is contained in:
Liangbin Lian 2025-07-17 11:00:41 +08:00
parent d2af980dd2
commit d2436c737f
3 changed files with 5 additions and 5 deletions

View File

@ -126,7 +126,7 @@
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
};
@ -135,7 +135,7 @@
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
};

View File

@ -87,7 +87,7 @@
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
};

View File

@ -245,7 +245,7 @@
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
realtek,led-data = <0xAC10>;
@ -255,7 +255,7 @@
&mdio1 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
realtek,led-data = <0xAC10>;